/****************************************************************************
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/****************************************************************************
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sbd_sqrt_fp_state_mach
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sbd_sqrt_fp_state_mach
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- state machine for sbd_sqrt_fp32
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- state machine for sbd_sqrt_fp32
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Copyright (C) 2005 Samuel Brown
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Copyright (C) 2005 Samuel Brown
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sam.brown@sbdesign.org
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sam.brown@sbdesign.org
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This library is free software; you can redistribute it and/or
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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****************************************************************************/
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****************************************************************************/
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module sbd_sqrt_fp_state_mach ( CLK,VAL_IN,INIT,LSR,ENR,ENL,EN_D,DLEFT,VAL_OUT );
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module sbd_sqrt_fp_state_mach ( CLK,VAL_IN,INIT,LSR,ENR,ENL,EN_D,DLEFT,VAL_OUT );
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parameter termval = 25;
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parameter termval = 25;
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input CLK;
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input CLK;
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input VAL_IN;
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input VAL_IN;
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output wire INIT;
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output wire INIT;
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output wire LSR;
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output wire LSR;
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output wire ENR;
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output wire ENR;
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output wire ENL;
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output wire ENL;
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output wire EN_D;
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output wire EN_D;
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output wire DLEFT;
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output wire DLEFT;
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output wire VAL_OUT;
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output wire VAL_OUT;
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wire begPulse;
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wire begPulse;
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reg terminate;
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reg terminate;
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reg [6:0] currentState;
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reg [6:0] currentState;
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wire [6:0] nextState;
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wire [6:0] nextState;
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reg [5:0] countValue;
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reg [5:0] countValue;
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reg val_state_reg;
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reg val_state_reg;
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wire active;
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wire active;
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initial
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initial
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begin
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begin
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currentState = 0;
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currentState = 0;
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countValue = 0;
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countValue = 0;
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val_state_reg = 0;
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val_state_reg = 0;
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end
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end
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assign INIT = currentState[6];
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assign INIT = currentState[6];
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assign LSR = currentState[5];
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assign LSR = currentState[5];
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assign ENR = currentState[4];
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assign ENR = currentState[4];
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assign ENL = currentState[3];
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assign ENL = currentState[3];
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assign EN_D = currentState[2];
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assign EN_D = currentState[2];
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assign DLEFT = currentState[1];
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assign DLEFT = currentState[1];
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assign nextState[6] = begPulse & ~terminate;
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assign nextState[6] = begPulse & ~terminate;
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assign nextState[5] = currentState[4]; // 31 or 25
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assign nextState[5] = currentState[4]; // 31 or 25
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assign nextState[4] = currentState[6] | (currentState[5] & ~terminate);
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assign nextState[4] = currentState[6] | (currentState[5] & ~terminate);
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assign nextState[3] = currentState[6] | (currentState[5] & ~terminate);
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assign nextState[3] = currentState[6] | (currentState[5] & ~terminate);
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assign nextState[2] = currentState[4] | (currentState[5] & ~terminate);
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assign nextState[2] = currentState[4] | (currentState[5] & ~terminate);
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assign nextState[1] = currentState[5] & ~terminate;
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assign nextState[1] = currentState[5] & ~terminate;
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assign nextState[0] = currentState[6] | (currentState[5] & ~terminate);
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assign nextState[0] = currentState[6] | (currentState[5] & ~terminate);
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always @ (posedge CLK)
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always @ (posedge CLK)
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begin:sqrtcount
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begin:sqrtcount
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if(begPulse) countValue <= 0;
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if(begPulse) countValue <= 0;
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else if(currentState[0]) countValue <= countValue + 1;
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else if(currentState[0]) countValue <= countValue + 1;
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end
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end
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always @ (posedge CLK)
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always @ (posedge CLK)
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begin:stateReg
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begin:stateReg
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currentState <= nextState;
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currentState <= nextState;
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end
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end
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always @ (countValue, begPulse)
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always @ (countValue, begPulse)
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begin:termassign
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begin:termassign
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if((countValue == termval) && ~begPulse) terminate = 1;
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if((countValue == termval) && ~begPulse) terminate = 1;
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else terminate = 0;
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else terminate = 0;
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end
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end
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//assign terminate = (countValue[4] & countValue[3] & ~countValue[2] & ~countValue[1] & countValue[0]) & ~begPulse;
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//assign terminate = (countValue[4] & countValue[3] & ~countValue[2] & ~countValue[1] & countValue[0]) & ~begPulse;
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//------------------- val in and out states ---------------------
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//------------------- val in and out states ---------------------
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always @ (posedge CLK)
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always @ (posedge CLK)
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begin:val_state_register
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begin:val_state_register
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val_state_reg <= active & ~VAL_OUT;
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val_state_reg <= active & ~VAL_OUT;
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end
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end
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assign begPulse = VAL_IN & ~val_state_reg;
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assign begPulse = VAL_IN & ~val_state_reg;
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assign active = begPulse | val_state_reg;
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assign active = begPulse | val_state_reg;
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assign VAL_OUT = terminate & active;
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assign VAL_OUT = terminate & active;
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endmodule
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endmodule
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