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Wishbone SD Card Controller IP Core
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Wishbone SD Card Controller IP Core
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===================================
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===================================
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The Wishbone SD Card Controller IP Core is MMC/SD communication controller designed to be
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The Wishbone SD Card Controller IP Core is MMC/SD communication controller designed to be
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used in a System-on-Chip. IP core provides simple interface for any CPU with Wishbone
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used in a System-on-Chip. IP core provides simple interface for any CPU with Wishbone
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bus. The communication between the MMC/SD card controller and MMC/SD card is performed
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bus. The communication between the MMC/SD card controller and MMC/SD card is performed
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according to the MMC/SD protocol.
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according to the MMC/SD protocol.
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Introduction
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Introduction
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------------
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------------
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This core is based on the "sd card controller" project from
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This core is based on the "sd card controller" project from
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http://opencores.org/project,sdcard_mass_storage_controller
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http://opencores.org/project,sdcard_mass_storage_controller
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but has been largely rewritten. A lot of effort has been made
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but has been largely rewritten. A lot of effort has been made
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to make the core more generic and easily usable
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to make the core more generic and easily usable
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with OSs like Linux.
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with OSs like Linux.
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- data transfer commands are not fixed
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- data transfer commands are not fixed
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- data transfer block size is configurable
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- data transfer block size is configurable
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- multiple block transfer support
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- multiple block transfer support
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- R2 responses (136 bit) support
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- R2 responses (136 bit) support
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Features
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Features
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--------
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--------
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The MMC/SD card controller provides following features:
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The MMC/SD card controller provides following features:
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- 1- or 4-bit MMC/SD mode (does not support SPI mode),
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- 1- or 4-bit MMC/SD mode (does not support SPI mode),
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- 32-bit Wishbone interface,
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- 32-bit Wishbone interface,
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- DMA engine for data transfers,
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- DMA engine for data transfers,
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- Interrupt generation on completion of data and command transactions,
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- Interrupt generation on completion of data and command transactions,
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- Configurable data transfer block size,
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- Configurable data transfer block size,
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- Support for any command code (including multiple data block tranfser),
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- Support for any command code (including multiple data block tranfser),
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- Support for R1, R1b, R2(136-bit), R3, R6 and R7 responses.
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- Support for R1, R1b, R2(136-bit), R3, R6 and R7 responses.
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Documentation
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Documentation
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-------------
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-------------
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The documentation is located in the doc/ directory.
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The documentation is located in the doc/ directory.
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Examples
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Examples
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--------
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--------
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A sample ORPSoC project that make use of this core is located at:
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A sample ORPSoC project that make use of this core is located at:
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https://github.com/mczerski/orpsoc-de0_nano
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https://github.com/mczerski/orpsoc-de0_nano
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The project is based on de0_nano board with custom made expansion board
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The project is based on de0_nano board with custom made expansion board
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with SD Card connector.
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with SD Card connector.
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There is also u-boot project port for this board located at:
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There is also u-boot project port for this board located at:
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https://github.com/mczerski/u-boot
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https://github.com/mczerski/u-boot
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This u-boot project contains driver for Wishbone SD Card Controller IP Core
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This u-boot project contains driver for Wishbone SD Card Controller IP Core
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and can be configured for de0_nano board (with custom made expansion board).
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and can be configured for de0_nano board (with custom made expansion board).
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Also in the plan is the driver for Linux. The initial work can be found at:
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Also in the plan is the driver for Linux. The initial work can be found at:
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https://bitbucket.org/rozpruwacz/linux-openrisc
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https://github.com/mczerski/linux - de0_nano branch
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the driver is named ocsdc and is located in drivers/mmc/host directory.
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the driver is named ocsdc and is located in drivers/mmc/host directory.
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TODO:
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-----
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- top level testbench cleanup (sd_controller_top_tb.sv)
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- rx/tx fifo treshold to do block transfers rather than many signle word transfers
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- maybe one fifo rathen than two fifos (rx and tx) would suffice since the transfer
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between card and controller is always half-duplex
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- read only and card detect signals support
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- timeout watchdog for data transfers
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