//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// WISHBONE SD Card Controller IP Core ////
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//// WISHBONE SD Card Controller IP Core ////
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//// ////
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//// ////
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//// sd_cmd_serial_host_tb.sv ////
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//// sd_cmd_serial_host_tb.sv ////
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//// ////
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//// ////
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//// This file is part of the WISHBONE SD Card ////
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//// This file is part of the WISHBONE SD Card ////
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//// Controller IP Core project ////
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//// Controller IP Core project ////
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//// http://www.opencores.org/cores/xxx/ ////
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//// http://opencores.org/project,sd_card_controller ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// testbench for sd_cmd_serial_host module ////
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//// testbench for sd_cmd_serial_host module ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Marek Czerski, ma.czerski@gmail.com ////
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//// - Marek Czerski, ma.czerski@gmail.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2013 Authors ////
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//// Copyright (C) 2013 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module sd_cmd_serial_host_tb();
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module sd_cmd_serial_host_tb();
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parameter SD_TCLK = 20; // 50 MHz -> timescale 1ns
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parameter SD_TCLK = 20; // 50 MHz -> timescale 1ns
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parameter CMD_IDLE = 1'b1;
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parameter CMD_IDLE = 1'b1;
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parameter CMD_START = 1'b0;
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parameter CMD_START = 1'b0;
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parameter CMD_END = 1'b1;
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parameter CMD_END = 1'b1;
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//---------------Input ports---------------
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//---------------Input ports---------------
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reg sd_clk;
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reg sd_clk;
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reg rst;
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reg rst;
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reg [1:0] setting_i;
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reg [1:0] setting_i;
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reg [39:0] cmd_i;
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reg [39:0] cmd_i;
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reg start_i;
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reg start_i;
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reg cmd_dat_i;
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reg cmd_dat_i;
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//---------------Output ports---------------
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//---------------Output ports---------------
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wire cmd_dat_tri;
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wire cmd_dat_tri;
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wire [119:0] response_o;
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wire [119:0] response_o;
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//wire ack_o;
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//wire ack_o;
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wire finish_o;
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wire finish_o;
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wire crc_ok_o;
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wire crc_ok_o;
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wire index_ok_o;
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wire index_ok_o;
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wire cmd_oe_o;
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wire cmd_oe_o;
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wire cmd_out_o;
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wire cmd_out_o;
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wire [39:0] command = 40'h0123456786;
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wire [39:0] command = 40'h0123456786;
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wire [127:0] response = 128'h0156789abcdef0123456789abcdef012;
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wire [127:0] response = 128'h0156789abcdef0123456789abcdef012;
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function integer crc7;
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function integer crc7;
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input integer crc_in;
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input integer crc_in;
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input bit inb;
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input bit inb;
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begin
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begin
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inb = inb ^ crc_in[0];
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inb = inb ^ crc_in[0];
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crc7 = crc_in >> 1;
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crc7 = crc_in >> 1;
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crc7 = crc7 ^ (7'h48 & {7{inb}});
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crc7 = crc7 ^ (7'h48 & {7{inb}});
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end
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end
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endfunction
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endfunction
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task sd_card_receive;
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task sd_card_receive;
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integer crc, i;
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integer crc, i;
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reg [39:0] cmd;
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reg [39:0] cmd;
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reg [6:0] crc_in;
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reg [6:0] crc_in;
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begin
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begin
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crc = 0;
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crc = 0;
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//wait for transmission start
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//wait for transmission start
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wait (cmd_oe_o == 1);
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wait (cmd_oe_o == 1);
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#(SD_TCLK/2);
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#(SD_TCLK/2);
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//get command bits
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//get command bits
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for (i=39; i>=0; i--) begin
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for (i=39; i>=0; i--) begin
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cmd[i] = cmd_out_o;
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cmd[i] = cmd_out_o;
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crc = crc7(crc, cmd_out_o);
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crc = crc7(crc, cmd_out_o);
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assert(cmd_oe_o == 1);
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assert(cmd_oe_o == 1);
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#SD_TCLK;
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#SD_TCLK;
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end
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end
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assert(cmd == command);
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assert(cmd == command);
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for (i=0; i<7; i++) begin
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for (i=0; i<7; i++) begin
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crc_in[i] = cmd_out_o;
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crc_in[i] = cmd_out_o;
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assert(cmd_oe_o == 1);
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assert(cmd_oe_o == 1);
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#SD_TCLK;
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#SD_TCLK;
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end
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end
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assert(crc_in == crc);
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assert(crc_in == crc);
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assert(cmd_out_o == CMD_END);
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assert(cmd_out_o == CMD_END);
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assert(cmd_oe_o == 1);
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assert(cmd_oe_o == 1);
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#SD_TCLK;
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#SD_TCLK;
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assert(cmd_oe_o == 0);
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assert(cmd_oe_o == 0);
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end
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end
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endtask
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endtask
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task sd_card_send;
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task sd_card_send;
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input long_resp;
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input long_resp;
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integer crc, i, loop_end;
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integer crc, i, loop_end;
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begin
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begin
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crc = 0;
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crc = 0;
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if (long_resp) loop_end = 0;
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if (long_resp) loop_end = 0;
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else loop_end = 127-39;
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else loop_end = 127-39;
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for (i=127; i>=loop_end; i--) begin
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for (i=127; i>=loop_end; i--) begin
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cmd_dat_i = response[i];
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cmd_dat_i = response[i];
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if (!long_resp || i < 120)
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if (!long_resp || i < 120)
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crc = crc7(crc, response[i]);
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crc = crc7(crc, response[i]);
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assert(cmd_oe_o == 0);
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assert(cmd_oe_o == 0);
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#SD_TCLK;
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#SD_TCLK;
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end
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end
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for (i=0; i<7; i++) begin
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for (i=0; i<7; i++) begin
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cmd_dat_i = crc[i];
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cmd_dat_i = crc[i];
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assert(cmd_oe_o == 0);
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assert(cmd_oe_o == 0);
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#SD_TCLK;
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#SD_TCLK;
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end
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end
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cmd_dat_i = CMD_END;
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cmd_dat_i = CMD_END;
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assert(cmd_oe_o == 0);
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assert(cmd_oe_o == 0);
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#SD_TCLK;
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#SD_TCLK;
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cmd_dat_i = CMD_IDLE;
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cmd_dat_i = CMD_IDLE;
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end
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end
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endtask
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endtask
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sd_cmd_serial_host cmd_serial_host_dut(
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sd_cmd_serial_host cmd_serial_host_dut(
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.sd_clk (sd_clk),
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.sd_clk (sd_clk),
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.rst (rst),
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.rst (rst),
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.setting_i (setting_i),
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.setting_i (setting_i),
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.cmd_i (cmd_i),
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.cmd_i (cmd_i),
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.start_i (start_i),
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.start_i (start_i),
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//.ack_i (ack_i),
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//.ack_i (ack_i),
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.finish_o (finish_o),
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.finish_o (finish_o),
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//.ack_o (ack_o),
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//.ack_o (ack_o),
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.response_o (response_o),
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.response_o (response_o),
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.crc_ok_o (crc_ok_o),
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.crc_ok_o (crc_ok_o),
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.index_ok_o (index_ok_o),
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.index_ok_o (index_ok_o),
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.cmd_dat_i (cmd_dat_tri),
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.cmd_dat_i (cmd_dat_tri),
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.cmd_out_o (cmd_out_o),
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.cmd_out_o (cmd_out_o),
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.cmd_oe_o (cmd_oe_o)
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.cmd_oe_o (cmd_oe_o)
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);
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);
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assign cmd_dat_tri = cmd_oe_o ? cmd_out_o : cmd_dat_i;
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assign cmd_dat_tri = cmd_oe_o ? cmd_out_o : cmd_dat_i;
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// Generating WB_CLK_I clock
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// Generating WB_CLK_I clock
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always
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always
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begin
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begin
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sd_clk=0;
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sd_clk=0;
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forever #(SD_TCLK/2) sd_clk = ~sd_clk;
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forever #(SD_TCLK/2) sd_clk = ~sd_clk;
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end
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end
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initial
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initial
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begin
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begin
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rst = 1;
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rst = 1;
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setting_i = 0;
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setting_i = 0;
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cmd_i = 1;
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cmd_i = 1;
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start_i = 0;
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start_i = 0;
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//ack_i = 0;
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//ack_i = 0;
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cmd_dat_i = CMD_IDLE;
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cmd_dat_i = CMD_IDLE;
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$display("sd_cmd_serial_host_tb start ...");
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$display("sd_cmd_serial_host_tb start ...");
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#(3*SD_TCLK);
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#(3*SD_TCLK);
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rst = 0;
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rst = 0;
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assert(finish_o == 0);
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assert(finish_o == 0);
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//assert(ack_o == 0);
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//assert(ack_o == 0);
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assert(crc_ok_o == 0);
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assert(crc_ok_o == 0);
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assert(index_ok_o == 0);
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assert(index_ok_o == 0);
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assert(cmd_out_o == 1);
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assert(cmd_out_o == 1);
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assert(cmd_oe_o == 1);
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assert(cmd_oe_o == 1);
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#SD_TCLK;
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#SD_TCLK;
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assert(finish_o == 0);
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assert(finish_o == 0);
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//assert(ack_o == 0);
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//assert(ack_o == 0);
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assert(crc_ok_o == 0);
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assert(crc_ok_o == 0);
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assert(index_ok_o == 0);
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assert(index_ok_o == 0);
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assert(cmd_out_o == 1);
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assert(cmd_out_o == 1);
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assert(cmd_oe_o == 1);
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assert(cmd_oe_o == 1);
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#(65*SD_TCLK); //INIT_DELAY
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#(65*SD_TCLK); //INIT_DELAY
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assert(finish_o == 0);
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assert(finish_o == 0);
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//assert(ack_o == 1);
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//assert(ack_o == 1);
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assert(crc_ok_o == 0);
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assert(crc_ok_o == 0);
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assert(index_ok_o == 0);
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assert(index_ok_o == 0);
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assert(cmd_oe_o == 0);
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assert(cmd_oe_o == 0);
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//tests with normal response (check index, check crc)
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//tests with normal response (check index, check crc)
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//tests with long response (check crc)
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//tests with long response (check crc)
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//cmd without response
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//cmd without response
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setting_i = {2'h0};
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setting_i = {2'h0};
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cmd_i <= command;
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cmd_i <= command;
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start_i <= 1'b1;
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start_i <= 1'b1;
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#SD_TCLK;
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#SD_TCLK;
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setting_i = 0;
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setting_i = 0;
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cmd_i <= 0;
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cmd_i <= 0;
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start_i <= 0;
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start_i <= 0;
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fork
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fork
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sd_card_receive;
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sd_card_receive;
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begin
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begin
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wait(finish_o == 1);
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wait(finish_o == 1);
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#(SD_TCLK/2);
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#(SD_TCLK/2);
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assert(crc_ok_o == 0);
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assert(crc_ok_o == 0);
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assert(index_ok_o == 0);
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assert(index_ok_o == 0);
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end
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end
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join
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join
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//cmd with r1 response
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//cmd with r1 response
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setting_i = {2'h1};
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setting_i = {2'h1};
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cmd_i <= command;
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cmd_i <= command;
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start_i <= 1'b1;
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start_i <= 1'b1;
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#SD_TCLK;
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#SD_TCLK;
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setting_i = 0;
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setting_i = 0;
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cmd_i <= 0;
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cmd_i <= 0;
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start_i <= 0;
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start_i <= 0;
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fork
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fork
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begin
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begin
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sd_card_receive;
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sd_card_receive;
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assert(finish_o == 0);
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assert(finish_o == 0);
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sd_card_send(0);
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sd_card_send(0);
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end
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end
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begin
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begin
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wait(finish_o == 1);
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wait(finish_o == 1);
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#(SD_TCLK/2);
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#(SD_TCLK/2);
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assert(response_o[119:88] == response[119:88]);
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assert(response_o[119:88] == response[119:88]);
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assert(crc_ok_o == 1);
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assert(crc_ok_o == 1);
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assert(index_ok_o == 1);
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assert(index_ok_o == 1);
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end
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end
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join
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join
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//cmd with r2 response
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//cmd with r2 response
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setting_i = {2'h3};
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setting_i = {2'h3};
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cmd_i <= command;
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cmd_i <= command;
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start_i <= 1'b1;
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start_i <= 1'b1;
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#SD_TCLK;
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#SD_TCLK;
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setting_i = 0;
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setting_i = 0;
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cmd_i <= 0;
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cmd_i <= 0;
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start_i <= 0;
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start_i <= 0;
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fork
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fork
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begin
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begin
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sd_card_receive;
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sd_card_receive;
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assert(finish_o == 0);
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assert(finish_o == 0);
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sd_card_send(1);
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sd_card_send(1);
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end
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end
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begin
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begin
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wait(finish_o == 1);
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wait(finish_o == 1);
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#(SD_TCLK/2);
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#(SD_TCLK/2);
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assert(response_o == response[119:0]);
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assert(response_o == response[119:0]);
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assert(crc_ok_o == 1);
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assert(crc_ok_o == 1);
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assert(index_ok_o == 1);
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assert(index_ok_o == 1);
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end
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end
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join
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join
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#(1000*SD_TCLK) $display("sd_cmd_serial_host_tb finish ...");
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#(1000*SD_TCLK) $display("sd_cmd_serial_host_tb finish ...");
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$finish;
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$finish;
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end
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end
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