//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// WISHBONE SD Card Controller IP Core ////
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//// WISHBONE SD Card Controller IP Core ////
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//// ////
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//// ////
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//// sd_controller_wb_tb.sv ////
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//// sd_controller_wb_tb.sv ////
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//// ////
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//// ////
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//// This file is part of the WISHBONE SD Card ////
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//// This file is part of the WISHBONE SD Card ////
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//// Controller IP Core project ////
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//// Controller IP Core project ////
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//// http://www.opencores.org/cores/xxx/ ////
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//// http://opencores.org/project,sd_card_controller ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// testbench for sd_controller_wb module ////
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//// testbench for sd_controller_wb module ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Marek Czerski, ma.czerski@gmail.com ////
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//// - Marek Czerski, ma.czerski@gmail.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2013 Authors ////
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//// Copyright (C) 2013 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
|
//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`include "sd_defines.h"
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`include "sd_defines.h"
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|
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module sd_controller_wb_tb();
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module sd_controller_wb_tb();
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parameter TCLK = 20; // 50 MHz -> timescale 1ns
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parameter TCLK = 20; // 50 MHz -> timescale 1ns
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|
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reg wb_clk_i;
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reg wb_clk_i;
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reg wb_rst_i;
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reg wb_rst_i;
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reg [31:0] wb_dat_i;
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reg [31:0] wb_dat_i;
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wire [31:0] wb_dat_o;
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wire [31:0] wb_dat_o;
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reg [7:0] wb_adr_i;
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reg [7:0] wb_adr_i;
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reg [3:0] wb_sel_i;
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reg [3:0] wb_sel_i;
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reg wb_we_i;
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reg wb_we_i;
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reg wb_cyc_i;
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reg wb_cyc_i;
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reg wb_stb_i;
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reg wb_stb_i;
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wire wb_ack_o;
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wire wb_ack_o;
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wire cmd_start;
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wire cmd_start;
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wire [31:0] argument_reg;
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wire [31:0] argument_reg;
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wire [`CMD_REG_SIZE-1:0] command_reg;
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wire [`CMD_REG_SIZE-1:0] command_reg;
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reg [31:0] response_0_reg;
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reg [31:0] response_0_reg;
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reg [31:0] response_1_reg;
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reg [31:0] response_1_reg;
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reg [31:0] response_2_reg;
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reg [31:0] response_2_reg;
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reg [31:0] response_3_reg;
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reg [31:0] response_3_reg;
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wire [0:0] software_reset_reg;
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wire [0:0] software_reset_reg;
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wire [15:0] timeout_reg;
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wire [15:0] timeout_reg;
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wire [`BLKSIZE_W-1:0] block_size_reg;
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wire [`BLKSIZE_W-1:0] block_size_reg;
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wire [15:0] controll_setting_reg;
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wire [15:0] controll_setting_reg;
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reg [`INT_CMD_SIZE-1:0] cmd_int_status_reg;
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reg [`INT_CMD_SIZE-1:0] cmd_int_status_reg;
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wire [`INT_CMD_SIZE-1:0] cmd_int_enable_reg;
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wire [`INT_CMD_SIZE-1:0] cmd_int_enable_reg;
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wire [7:0] clock_divider_reg;
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wire [7:0] clock_divider_reg;
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reg [`INT_DATA_SIZE-1:0] data_int_status_reg;
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reg [`INT_DATA_SIZE-1:0] data_int_status_reg;
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wire [`INT_DATA_SIZE-1:0] data_int_enable_reg;
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wire [`INT_DATA_SIZE-1:0] data_int_enable_reg;
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wire data_int_rst;
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wire data_int_rst;
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wire cmd_int_rst;
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wire cmd_int_rst;
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wire [`BLKCNT_W-1:0]block_count_reg;
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wire [`BLKCNT_W-1:0]block_count_reg;
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wire [31:0] dma_addr_reg;
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wire [31:0] dma_addr_reg;
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|
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sd_controller_wb sd_controller_wb_dut(
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sd_controller_wb sd_controller_wb_dut(
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wb_clk_i,
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wb_clk_i,
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wb_rst_i,
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wb_rst_i,
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wb_dat_i,
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wb_dat_i,
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wb_dat_o,
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wb_dat_o,
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wb_adr_i,
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wb_adr_i,
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wb_sel_i,
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wb_sel_i,
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wb_we_i,
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wb_we_i,
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wb_cyc_i,
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wb_cyc_i,
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wb_stb_i,
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wb_stb_i,
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wb_ack_o,
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wb_ack_o,
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cmd_start,
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cmd_start,
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data_int_rst,
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data_int_rst,
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cmd_int_rst,
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cmd_int_rst,
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argument_reg,
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argument_reg,
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command_reg,
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command_reg,
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response_0_reg,
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response_0_reg,
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response_1_reg,
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response_1_reg,
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response_2_reg,
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response_2_reg,
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response_3_reg,
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response_3_reg,
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software_reset_reg,
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software_reset_reg,
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timeout_reg,
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timeout_reg,
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block_size_reg,
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block_size_reg,
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controll_setting_reg,
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controll_setting_reg,
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cmd_int_status_reg,
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cmd_int_status_reg,
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cmd_int_enable_reg,
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cmd_int_enable_reg,
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clock_divider_reg,
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clock_divider_reg,
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block_count_reg,
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block_count_reg,
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dma_addr_reg,
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dma_addr_reg,
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data_int_status_reg,
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data_int_status_reg,
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data_int_enable_reg
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data_int_enable_reg
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);
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);
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|
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// Generating wb_clk_i clock
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// Generating wb_clk_i clock
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always
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always
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begin
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begin
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wb_clk_i=0;
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wb_clk_i=0;
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forever #(TCLK/2) wb_clk_i = ~wb_clk_i;
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forever #(TCLK/2) wb_clk_i = ~wb_clk_i;
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end
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end
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task wb_write;
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task wb_write;
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input integer data;
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input integer data;
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input integer addr;
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input integer addr;
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begin
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begin
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//wait for falling edge of wb_clk_i
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//wait for falling edge of wb_clk_i
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wait(wb_clk_i == 1);
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wait(wb_clk_i == 1);
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wait(wb_clk_i == 0);
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wait(wb_clk_i == 0);
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wb_dat_i = data;
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wb_dat_i = data;
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wb_adr_i = addr;
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wb_adr_i = addr;
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wb_sel_i = 4'b1111;
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wb_sel_i = 4'b1111;
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wb_we_i = 1;
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wb_we_i = 1;
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wb_cyc_i = 1;
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wb_cyc_i = 1;
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wb_stb_i = 1;
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wb_stb_i = 1;
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wait(wb_ack_o == 1);
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wait(wb_ack_o == 1);
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wb_dat_i = 0;
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wb_dat_i = 0;
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wb_adr_i = 0;
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wb_adr_i = 0;
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wb_sel_i = 0;
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wb_sel_i = 0;
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wb_we_i = 0;
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wb_we_i = 0;
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wb_cyc_i = 0;
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wb_cyc_i = 0;
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wb_stb_i = 0;
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wb_stb_i = 0;
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|
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#(1.5*TCLK);
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#(1.5*TCLK);
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assert(wb_ack_o == 0);
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assert(wb_ack_o == 0);
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#TCLK;
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#TCLK;
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end
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end
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endtask
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endtask
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task wb_read_check;
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task wb_read_check;
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input integer data;
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input integer data;
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input integer addr;
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input integer addr;
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begin
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begin
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//wait for falling edge of wb_clk_i
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//wait for falling edge of wb_clk_i
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wait(wb_clk_i == 1);
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wait(wb_clk_i == 1);
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wait(wb_clk_i == 0);
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wait(wb_clk_i == 0);
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wb_adr_i = addr;
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wb_adr_i = addr;
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wb_sel_i = 4'b1111;
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wb_sel_i = 4'b1111;
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wb_we_i = 0;
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wb_we_i = 0;
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wb_cyc_i = 1;
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wb_cyc_i = 1;
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wb_stb_i = 1;
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wb_stb_i = 1;
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|
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wait(wb_ack_o == 1);
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wait(wb_ack_o == 1);
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wb_dat_i = 0;
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wb_dat_i = 0;
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wb_adr_i = 0;
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wb_adr_i = 0;
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wb_sel_i = 0;
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wb_sel_i = 0;
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wb_we_i = 0;
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wb_we_i = 0;
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wb_cyc_i = 0;
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wb_cyc_i = 0;
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wb_stb_i = 0;
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wb_stb_i = 0;
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assert(wb_dat_o == data);
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assert(wb_dat_o == data);
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#(1.5*TCLK);
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#(1.5*TCLK);
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assert(wb_ack_o == 0);
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assert(wb_ack_o == 0);
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#TCLK;
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#TCLK;
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end
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end
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endtask
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endtask
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initial
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initial
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begin
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begin
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wb_rst_i = 1;
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wb_rst_i = 1;
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wb_dat_i = 0;
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wb_dat_i = 0;
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wb_adr_i = 0;
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wb_adr_i = 0;
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wb_sel_i = 0;
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wb_sel_i = 0;
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wb_we_i = 0;
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wb_we_i = 0;
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wb_cyc_i = 0;
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wb_cyc_i = 0;
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wb_stb_i = 0;
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wb_stb_i = 0;
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response_0_reg = 0;
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response_0_reg = 0;
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response_1_reg = 0;
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response_1_reg = 0;
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response_2_reg = 0;
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response_2_reg = 0;
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response_3_reg = 0;
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response_3_reg = 0;
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cmd_int_status_reg = 0;
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cmd_int_status_reg = 0;
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data_int_status_reg = 0;
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data_int_status_reg = 0;
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#(3.2*TCLK);
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#(3.2*TCLK);
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wb_rst_i = 0;
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wb_rst_i = 0;
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#TCLK;
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#TCLK;
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$display("sd_controller_wb_tb start ...");
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$display("sd_controller_wb_tb start ...");
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assert(wb_dat_o == 0);
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assert(wb_dat_o == 0);
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assert(wb_ack_o == 0);
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assert(wb_ack_o == 0);
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assert(cmd_start == 0);
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assert(cmd_start == 0);
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assert(argument_reg == 0);
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assert(argument_reg == 0);
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assert(command_reg == 0);
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assert(command_reg == 0);
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assert(software_reset_reg == 0);
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assert(software_reset_reg == 0);
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assert(timeout_reg == 0);
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assert(timeout_reg == 0);
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assert(block_size_reg == `RESET_BLOCK_SIZE);
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assert(block_size_reg == `RESET_BLOCK_SIZE);
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assert(controll_setting_reg == 0);
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assert(controll_setting_reg == 0);
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assert(cmd_int_status_reg == 0);
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assert(cmd_int_status_reg == 0);
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assert(cmd_int_enable_reg == 0);
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assert(cmd_int_enable_reg == 0);
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assert(clock_divider_reg == `RESET_CLK_DIV);
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assert(clock_divider_reg == `RESET_CLK_DIV);
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assert(data_int_enable_reg == 0);
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assert(data_int_enable_reg == 0);
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assert(data_int_rst == 0);
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assert(data_int_rst == 0);
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assert(cmd_int_rst == 0);
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assert(cmd_int_rst == 0);
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assert(block_count_reg == 0);
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assert(block_count_reg == 0);
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assert(dma_addr_reg == 0);
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assert(dma_addr_reg == 0);
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//check argument register and cmd_start signal
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//check argument register and cmd_start signal
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fork
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fork
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begin
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begin
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wb_write(32'h01020304, `argument);
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wb_write(32'h01020304, `argument);
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assert(argument_reg == 32'h01020304);
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assert(argument_reg == 32'h01020304);
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end
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end
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begin
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begin
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wait(cmd_start == 1);
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wait(cmd_start == 1);
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#(1.1*TCLK);
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#(1.1*TCLK);
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assert(cmd_start == 0);
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assert(cmd_start == 0);
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end
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end
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join
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join
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//check command register
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//check command register
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wb_write(16'h0405, `command);
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wb_write(16'h0405, `command);
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assert(command_reg == 16'h0405);
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assert(command_reg == 16'h0405);
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//check response_0 register
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//check response_0 register
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response_0_reg = 32'h04050607;
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response_0_reg = 32'h04050607;
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wb_read_check(32'h04050607, `resp0);
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wb_read_check(32'h04050607, `resp0);
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|
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//check response_1 register
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//check response_1 register
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response_1_reg = 32'h05060708;
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response_1_reg = 32'h05060708;
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wb_read_check(32'h05060708, `resp1);
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wb_read_check(32'h05060708, `resp1);
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|
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//check response_2 register
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//check response_2 register
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response_2_reg = 32'h06070809;
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response_2_reg = 32'h06070809;
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wb_read_check(32'h06070809, `resp2);
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wb_read_check(32'h06070809, `resp2);
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|
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//check response_3 register
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//check response_3 register
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response_3_reg = 32'h0708090a;
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response_3_reg = 32'h0708090a;
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wb_read_check(32'h0708090a, `resp3);
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wb_read_check(32'h0708090a, `resp3);
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|
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//check controller register
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//check controller register
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wb_write(16'h0a0b, `controller);
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wb_write(16'h0a0b, `controller);
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assert(controll_setting_reg == 16'h0a0b);
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assert(controll_setting_reg == 16'h0a0b);
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|
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//check timeout register
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//check timeout register
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wb_write(16'h0b0c, `timeout);
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wb_write(16'h0b0c, `timeout);
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assert(timeout_reg == 16'h0b0c);
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assert(timeout_reg == 16'h0b0c);
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|
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//check clock_devider register
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//check clock_devider register
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wb_write(8'h0d, `clock_d);
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wb_write(8'h0d, `clock_d);
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assert(clock_divider_reg == 8'h0d);
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assert(clock_divider_reg == 8'h0d);
|
|
|
//check reset register
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//check reset register
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wb_write(1'h1, `reset);
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wb_write(1'h1, `reset);
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assert(software_reset_reg == 1'h1);
|
assert(software_reset_reg == 1'h1);
|
|
|
//check voltage register
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//check voltage register
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wb_read_check(8'b0000_111_1, `voltage);
|
wb_read_check(8'b0000_111_1, `voltage);
|
|
|
//check capability register
|
//check capability register
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wb_read_check(16'h0000, `capa);
|
wb_read_check(16'h0000, `capa);
|
|
|
//check cmd_isr register write
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//check cmd_isr register write
|
fork
|
fork
|
begin
|
begin
|
wb_write(32'h0, `cmd_isr);
|
wb_write(32'h0, `cmd_isr);
|
end
|
end
|
begin
|
begin
|
wait(cmd_int_rst == 1);
|
wait(cmd_int_rst == 1);
|
#(1.1*TCLK);
|
#(1.1*TCLK);
|
assert(cmd_int_rst == 0);
|
assert(cmd_int_rst == 0);
|
end
|
end
|
join
|
join
|
//check cmd_isr register read
|
//check cmd_isr register read
|
cmd_int_status_reg = 5'h1a;
|
cmd_int_status_reg = 5'h1a;
|
wb_read_check(5'h1a, `cmd_isr);
|
wb_read_check(5'h1a, `cmd_isr);
|
|
|
//check cmd_iser register
|
//check cmd_iser register
|
wb_write(5'h15, `cmd_iser);
|
wb_write(5'h15, `cmd_iser);
|
assert(cmd_int_enable_reg == 5'h15);
|
assert(cmd_int_enable_reg == 5'h15);
|
|
|
//check data_isr register write
|
//check data_isr register write
|
fork
|
fork
|
begin
|
begin
|
wb_write(32'h0, `data_isr);
|
wb_write(32'h0, `data_isr);
|
end
|
end
|
begin
|
begin
|
wait(data_int_rst == 1);
|
wait(data_int_rst == 1);
|
#(1.1*TCLK);
|
#(1.1*TCLK);
|
assert(data_int_rst == 0);
|
assert(data_int_rst == 0);
|
end
|
end
|
join
|
join
|
//check data_isr register read
|
//check data_isr register read
|
data_int_status_reg = 3'h6;
|
data_int_status_reg = 3'h6;
|
wb_read_check(3'h6, `data_isr);
|
wb_read_check(3'h6, `data_isr);
|
|
|
//check data_iser register
|
//check data_iser register
|
wb_write(3'h5, `data_iser);
|
wb_write(3'h5, `data_iser);
|
assert(data_int_enable_reg == 3'h5);
|
assert(data_int_enable_reg == 3'h5);
|
|
|
//check blksize register
|
//check blksize register
|
wb_write(12'habc, `blksize);
|
wb_write(12'habc, `blksize);
|
assert(block_size_reg == 12'habc);
|
assert(block_size_reg == 12'habc);
|
|
|
//check blkcnt register
|
//check blkcnt register
|
wb_write(16'h1011, `blkcnt);
|
wb_write(16'h1011, `blkcnt);
|
assert(block_count_reg == 16'h1011);
|
assert(block_count_reg == 16'h1011);
|
|
|
//check dst_src_addr register
|
//check dst_src_addr register
|
wb_write(32'h11121314, `dst_src_addr);
|
wb_write(32'h11121314, `dst_src_addr);
|
assert(dma_addr_reg == 32'h11121314);
|
assert(dma_addr_reg == 32'h11121314);
|
|
|
#(10*TCLK) $display("sd_controller_wb_tb finish ...");
|
#(10*TCLK) $display("sd_controller_wb_tb finish ...");
|
$finish;
|
$finish;
|
|
|
end
|
end
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endmodule
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endmodule
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