######################################################################
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######################################################################
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#### ####
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#### ####
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#### WISHBONE SD Card Controller IP Core ####
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#### WISHBONE SD Card Controller IP Core ####
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#### ####
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#### ####
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#### Makefile ####
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#### Makefile ####
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#### ####
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#### ####
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#### This file is part of the WISHBONE SD Card ####
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#### This file is part of the WISHBONE SD Card ####
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#### Controller IP Core project ####
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#### Controller IP Core project ####
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#### http://www.opencores.org/cores/xxx/ ####
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#### http://opencores.org/project,sd_card_controller ####
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#### ####
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#### ####
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#### Description ####
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#### Description ####
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#### Simulation makefile ####
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#### Simulation makefile ####
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#### ####
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#### ####
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#### Author(s): ####
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#### Author(s): ####
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#### - Marek Czerski, ma.czerski@gmail.com ####
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#### - Marek Czerski, ma.czerski@gmail.com ####
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#### ####
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#### ####
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######################################################################
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######################################################################
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#### ####
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#### ####
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#### Copyright (C) 2013 Authors ####
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#### Copyright (C) 2013 Authors ####
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#### ####
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#### ####
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#### This source file may be used and distributed without ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### the original copyright notice and the associated disclaimer. ####
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#### ####
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#### ####
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#### This source file is free software; you can redistribute it ####
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#### This source file is free software; you can redistribute it ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### Public License as published by the Free Software Foundation; ####
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#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### later version. ####
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#### later version. ####
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#### ####
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#### ####
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#### This source is distributed in the hope that it will be ####
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#### This source is distributed in the hope that it will be ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### details. ####
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#### details. ####
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#### ####
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#### ####
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#### You should have received a copy of the GNU Lesser General ####
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#### You should have received a copy of the GNU Lesser General ####
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#### Public License along with this source; if not, download it ####
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#### Public License along with this source; if not, download it ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### ####
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#### ####
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######################################################################
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######################################################################
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V ?= @
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V ?= @
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VCD ?= 0
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VCD ?= 0
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MODELSIM_DIR ?= /opt/altera/11.0/modelsim_ase
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MODELSIM_DIR ?= /opt/altera/11.0/modelsim_ase
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VCOM = $(MODELSIM_DIR)/bin/vcom
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VCOM = $(MODELSIM_DIR)/bin/vcom
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VLOG = $(MODELSIM_DIR)/bin/vlog
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VLOG = $(MODELSIM_DIR)/bin/vlog
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VOPT = $(MODELSIM_DIR)/bin/vopt
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VOPT = $(MODELSIM_DIR)/bin/vopt
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SCCOM = $(MODELSIM_DIR)/bin/sccom
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SCCOM = $(MODELSIM_DIR)/bin/sccom
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VLIB = $(MODELSIM_DIR)/bin/vlib
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VLIB = $(MODELSIM_DIR)/bin/vlib
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VMAP = $(MODELSIM_DIR)/bin/vmap
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VMAP = $(MODELSIM_DIR)/bin/vmap
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VSIM = $(MODELSIM_DIR)/bin/vsim
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VSIM = $(MODELSIM_DIR)/bin/vsim
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# Define path to each library
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# Define path to each library
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LIB_SV_STD = $(MODELSIM_DIR)/sv_std
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LIB_SV_STD = $(MODELSIM_DIR)/sv_std
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LIB_WORK = work
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LIB_WORK = work
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LIB_TEST = test
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LIB_TEST = test
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RUN_DIR = $(shell pwd)
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RUN_DIR = $(shell pwd)
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BIN_DIR = $(shell pwd)/../bin
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BIN_DIR = $(shell pwd)/../bin
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LOG_DIR = $(shell pwd)/../log
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LOG_DIR = $(shell pwd)/../log
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OUT_DIR = $(shell pwd)/../out
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OUT_DIR = $(shell pwd)/../out
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WORK_DIR = ../../../rtl/verilog
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WORK_DIR = ../../../rtl/verilog
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TEST_DIR = ../../../bench/verilog
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TEST_DIR = ../../../bench/verilog
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WORK_SOURCES = $(wildcard $(WORK_DIR)/*.v)
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WORK_SOURCES = $(wildcard $(WORK_DIR)/*.v)
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TEST_SOURCES = $(wildcard $(TEST_DIR)/*.sv) $(wildcard $(TEST_DIR)/*.v)
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TEST_SOURCES = $(wildcard $(TEST_DIR)/*.sv) $(wildcard $(TEST_DIR)/*.v)
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WORK_OBJECTS = $(shell echo $(WORK_SOURCES) | sed 's:$(WORK_DIR):./$(LIB_WORK):g' | sed 's:\.v:/_primary.dat:g')
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WORK_OBJECTS = $(shell echo $(WORK_SOURCES) | sed 's:$(WORK_DIR):./$(LIB_WORK):g' | sed 's:\.v:/_primary.dat:g')
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TEST_OBJECTS = $(shell echo $(TEST_SOURCES) | sed 's:$(TEST_DIR):./$(LIB_TEST):g' | sed 's:\.sv:/_primary.dat:g')
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TEST_OBJECTS = $(shell echo $(TEST_SOURCES) | sed 's:$(TEST_DIR):./$(LIB_TEST):g' | sed 's:\.sv:/_primary.dat:g')
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all: simulate
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all: simulate
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work_library: $(LIB_WORK) $(WORK_OBJECTS)
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work_library: $(LIB_WORK) $(WORK_OBJECTS)
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#./$(LIB_WORK)/%/_primary.dat: $(WORK_DIR)/%.v
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#./$(LIB_WORK)/%/_primary.dat: $(WORK_DIR)/%.v
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# @echo $@
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# @echo $@
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# $(V)$(VLOG) -work $(LIB_WORK) +incdir+$(WORK_DIR) -nocovercells -O0 $^
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# $(V)$(VLOG) -work $(LIB_WORK) +incdir+$(WORK_DIR) -nocovercells -O0 $^
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$(WORK_OBJECTS): $(WORK_SOURCES)
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$(WORK_OBJECTS): $(WORK_SOURCES)
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$(V)$(VLOG) -work $(LIB_WORK) +incdir+$(WORK_DIR) -nocovercells -O0 $?
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$(V)$(VLOG) -work $(LIB_WORK) +incdir+$(WORK_DIR) -nocovercells -O0 $?
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$(LIB_WORK) :
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$(LIB_WORK) :
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$(V)echo "creating library $@ ..."
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$(V)echo "creating library $@ ..."
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$(V)$(VLIB) $(LIB_WORK)
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$(V)$(VLIB) $(LIB_WORK)
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$(V)$(VMAP) $(LIB_WORK) $(LIB_WORK)
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$(V)$(VMAP) $(LIB_WORK) $(LIB_WORK)
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test_library: $(LIB_TEST) $(TEST_OBJECTS)
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test_library: $(LIB_TEST) $(TEST_OBJECTS)
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$(TEST_OBJECTS): $(TEST_SOURCES)
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$(TEST_OBJECTS): $(TEST_SOURCES)
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$(V)$(VLOG) -work $(LIB_TEST) +incdir+$(WORK_DIR) +incdir+$(TEST_DIR) -nocovercells -O0 $?
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$(V)$(VLOG) -work $(LIB_TEST) +incdir+$(WORK_DIR) +incdir+$(TEST_DIR) -nocovercells -O0 $?
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$(LIB_TEST) :
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$(LIB_TEST) :
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$(V)echo "creating library $@ ..."
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$(V)echo "creating library $@ ..."
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$(V)$(VLIB) $(LIB_TEST)
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$(V)$(VLIB) $(LIB_TEST)
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$(V)$(VMAP) $(LIB_TEST) $(LIB_TEST)
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$(V)$(VMAP) $(LIB_TEST) $(LIB_TEST)
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compile: work_library test_library
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compile: work_library test_library
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TESTBENCH_SOURCES = $(shell ls $(TEST_DIR)/*_tb.sv)
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TESTBENCH_SOURCES = $(shell ls $(TEST_DIR)/*_tb.sv)
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TESTBENCHES = $(shell echo $(TESTBENCH_SOURCES) | sed 's:$(TEST_DIR)/::g' | sed 's:\.sv::g')
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TESTBENCHES = $(shell echo $(TESTBENCH_SOURCES) | sed 's:$(TEST_DIR)/::g' | sed 's:\.sv::g')
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ifeq ($(VCD), 1)
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ifeq ($(VCD), 1)
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CLI_STARTUP_FILE = $(BIN_DIR)/vcd_startup.do
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CLI_STARTUP_FILE = $(BIN_DIR)/vcd_startup.do
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VCD_DIR = $(OUT_DIR)
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VCD_DIR = $(OUT_DIR)
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else
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else
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CLI_STARTUP_FILE = $(BIN_DIR)/cli_startup.do
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CLI_STARTUP_FILE = $(BIN_DIR)/cli_startup.do
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endif
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endif
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$(OUT_DIR):
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$(OUT_DIR):
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$(V)mkdir $@
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$(V)mkdir $@
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$(LOG_DIR):
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$(LOG_DIR):
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$(V)mkdir $@
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$(V)mkdir $@
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%_tb: $(LOG_DIR) $(VCD_DIR) compile
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%_tb: $(LOG_DIR) $(VCD_DIR) compile
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$(V)$(VSIM) -c -L $(RUN_DIR)/$(LIB_WORK) -do $(CLI_STARTUP_FILE) $(LIB_TEST).$@
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$(V)$(VSIM) -c -L $(RUN_DIR)/$(LIB_WORK) -do $(CLI_STARTUP_FILE) $(LIB_TEST).$@
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$(V)if [ $(VCD) = 1 ]; then mv tmp.vcd $(OUT_DIR)/$@.vcd; fi
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$(V)if [ $(VCD) = 1 ]; then mv tmp.vcd $(OUT_DIR)/$@.vcd; fi
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simulate: $(TESTBENCHES)
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simulate: $(TESTBENCHES)
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modelsim: compile
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modelsim: compile
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$(V)$(VSIM) -lib $(LIB_WORK)
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$(V)$(VSIM) -lib $(LIB_WORK)
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%_tb_gui: $(LOG_DIR) compile
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%_tb_gui: $(LOG_DIR) compile
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$(V)$(VSIM) -L $(RUN_DIR)/$(LIB_WORK) -do $(BIN_DIR)/gui_startup.do $(LIB_TEST).$(shell echo $@ | sed 's:_gui::')
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$(V)$(VSIM) -L $(RUN_DIR)/$(LIB_WORK) -do $(BIN_DIR)/gui_startup.do $(LIB_TEST).$(shell echo $@ | sed 's:_gui::')
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print_work_sources:
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print_work_sources:
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$(V)@echo $(WORK_SOURCES)
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$(V)@echo $(WORK_SOURCES)
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print_test_sources:
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print_test_sources:
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$(V)@echo $(TEST_SOURCES)
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$(V)@echo $(TEST_SOURCES)
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print_work_objects:
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print_work_objects:
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$(V)@echo $(WORK_OBJECTS)
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$(V)@echo $(WORK_OBJECTS)
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print_testbenches:
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print_testbenches:
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$(V)@echo $(TESTBENCHES)
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$(V)@echo $(TESTBENCHES)
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clean:
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clean:
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$(V)rm -rfv $(LIB_WORK)
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$(V)rm -rfv $(LIB_WORK)
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$(V)rm -rfv $(LIB_TEST)
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$(V)rm -rfv $(LIB_TEST)
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$(V)rm -rfv $(LOG_DIR)
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$(V)rm -rfv $(LOG_DIR)
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$(V)rm -rfv $(OUT_DIR)
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$(V)rm -rfv $(OUT_DIR)
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$(V)rm -fv modelsim.ini *.wlf transcript
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$(V)rm -fv modelsim.ini *.wlf transcript
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