//`include "timescale.v"
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//`include "timescale.v"
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`include "SD_defines.v"
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`include "sd_defines.v"
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`define tTLH 10 //Clock rise time
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`define tTLH 10 //Clock rise time
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`define tHL 10 //Clock fall time
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`define tHL 10 //Clock fall time
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`define tISU 6 //Input setup time
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`define tISU 6 //Input setup time
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`define tIH 0 //Input hold time
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`define tIH 0 //Input hold time
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`define tODL 14 //Output delay
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`define tODL 14 //Output delay
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`define DLY_TO_OUTP 47
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`define DLY_TO_OUTP 47
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`define BLOCKSIZE 512
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`define BLOCKSIZE 512
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`define MEMSIZE 2048 // 4 block
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`define MEMSIZE 24643590 // 2mb block
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`define BLOCK_BUFFER_SIZE 1
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`define BLOCK_BUFFER_SIZE 1
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`define TIME_BUSY 64
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`define TIME_BUSY 63
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`define PRG 7
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`define PRG 7
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`define RCV 6
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`define RCV 6
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`define DATAS 5
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`define DATAS 5
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`define TRAN 4
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`define TRAN 4
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module sdModel(
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module sdModel(
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input sdClk,
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input sdClk,
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tri cmd,
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tri cmd,
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tri [3:0] dat
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tri [3:0] dat
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);
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);
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reg oeCmd;
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reg oeCmd;
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reg oeDat;
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reg oeDat;
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reg cmdOut;
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reg cmdOut;
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reg [3:0] datOut;
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reg [3:0] datOut;
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reg [10:0] transf_cnt;
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reg [10:0] transf_cnt;
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reg [5:0] lastCMD;
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reg [5:0] lastCMD;
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reg cardIdentificationState;
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reg cardIdentificationState;
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reg CardTransferActive;
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reg CardTransferActive;
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reg [2:0] BusWidth;
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reg [2:0] BusWidth;
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assign cmd = oeCmd ? cmdOut : 1'bz;
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assign cmd = oeCmd ? cmdOut : 1'bz;
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assign dat = oeDat ? datOut : 4'bz;
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assign dat = oeDat ? datOut : 4'bz;
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reg InbuffStatus;
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reg InbuffStatus;
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reg [31:0] BlockAddr;
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reg [31:0] BlockAddr;
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reg [7:0] Inbuff [0:511];
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reg [7:0] Inbuff [0:511];
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reg [7:0] FLASHmem [0:`MEMSIZE];
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reg [7:0] FLASHmem [0:`MEMSIZE];
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reg [46:0]inCmd;
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reg [46:0]inCmd;
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reg [5:0]cmdRead;
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reg [5:0]cmdRead;
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reg [7:0] cmdWrite;
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reg [7:0] cmdWrite;
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reg crcIn;
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reg crcIn;
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reg crcEn;
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reg crcEn;
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reg crcRst;
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reg crcRst;
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reg [31:0] CardStatus;
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reg [31:0] CardStatus;
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reg [15:0] RCA;
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reg [15:0] RCA;
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reg [31:0] OCR;
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reg [31:0] OCR;
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reg [120:0] CID;
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reg [120:0] CID;
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reg [120:0] CSD;
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reg Busy; //0 when busy
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reg Busy; //0 when busy
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wire [6:0] crcOut;
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wire [6:0] crcOut;
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reg [4:0] crc_c;
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reg [4:0] crc_c;
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reg [3:0] CurrentState;
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reg [3:0] CurrentState;
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reg [3:0] DataCurrentState;
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reg [3:0] DataCurrentState;
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`define RCASTART 16'h20
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`define RCASTART 16'h2000
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`define OCRSTART 32'hff8000
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`define OCRSTART 32'hff8000
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`define STATUSSTART 32'h0
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`define STATUSSTART 32'h0
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`define CIDSTART 128'h00ffffffddddddddaaaaaaaa99999999 //Just some random data not really usefull anyway
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`define CIDSTART 128'hffffffddddddddaaaaaaaa99999999 //Just some random data not really usefull anyway
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`define CSDSTART 128'hadaeeeddddddddaaaaaaaa12345678
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`define outDelay 4
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`define outDelay 4
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reg [2:0] outDelayCnt;
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reg [2:0] outDelayCnt;
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reg [9:0] flash_write_cnt;
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reg [9:0] flash_write_cnt;
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reg [8:0] flash_blockwrite_cnt;
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reg [8:0] flash_blockwrite_cnt;
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parameter SIZE = 10;
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parameter SIZE = 10;
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parameter CONTENT_SIZE = 40;
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parameter CONTENT_SIZE = 40;
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parameter
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parameter
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IDLE = 10'b0000_0000_01,
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IDLE = 10'b0000_0000_01,
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READ_CMD = 10'b0000_0000_10,
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READ_CMD = 10'b0000_0000_10,
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ANALYZE_CMD = 10'b0000_0001_00,
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ANALYZE_CMD = 10'b0000_0001_00,
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SEND_CMD = 10'b0000_0010_00;
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SEND_CMD = 10'b0000_0010_00;
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reg [SIZE-1:0] state;
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reg [SIZE-1:0] state;
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reg [SIZE-1:0] next_state;
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reg [SIZE-1:0] next_state;
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parameter
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parameter
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DATA_IDLE =10'b0000_0000_01,
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DATA_IDLE =10'b0000_0000_01,
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READ_WAITS =10'b0000_0000_10,
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READ_WAITS =10'b0000_0000_10,
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READ_DATA = 10'b0000_0001_00,
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READ_DATA = 10'b0000_0001_00,
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WRITE_FLASH =10'b0000_0010_00,
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WRITE_FLASH =10'b0000_0010_00,
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WRITE_DATA =10'b0000_0100_00;
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WRITE_DATA =10'b0000_0100_00;
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parameter okcrctoken = 4'b0101;
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parameter okcrctoken = 4'b0101;
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parameter invalidcrctoken = 4'b1111;
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parameter invalidcrctoken = 4'b1111;
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reg [SIZE-1:0] dataState;
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reg [SIZE-1:0] dataState;
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reg [SIZE-1:0] next_datastate;
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reg [SIZE-1:0] next_datastate;
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reg ValidCmd;
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reg ValidCmd;
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reg inValidCmd;
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reg inValidCmd;
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reg [7:0] response_S;
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reg [7:0] response_S;
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reg [135:0] response_CMD;
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reg [135:0] response_CMD;
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integer responseType;
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integer responseType;
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reg [9:0] block_cnt;
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reg [9:0] block_cnt;
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reg wptr;
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reg wptr;
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reg crc_ok;
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reg crc_ok;
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reg [3:0] last_din;
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reg [3:0] last_din;
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reg crcDat_rst;
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reg crcDat_rst;
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reg mult_read;
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reg mult_write;
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reg crcDat_en;
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reg crcDat_en;
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reg [3:0] crcDat_in;
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reg [3:0] crcDat_in;
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wire [15:0] crcDat_out [3:0];
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wire [15:0] crcDat_out [3:0];
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genvar i;
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genvar i;
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generate
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generate
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for(i=0; i<4; i=i+1) begin:CRC_16_gen
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for(i=0; i<4; i=i+1) begin:CRC_16_gen
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SD_CRC_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]);
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sd_crc_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]);
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end
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end
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endgenerate
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endgenerate
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SD_CRC_7 CRC_7(
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sd_crc_7 crc_7(
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crcIn,
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crcIn,
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crcEn,
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crcEn,
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sdClk,
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sdClk,
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crcRst,
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crcRst,
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crcOut);
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crcOut);
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reg stop;
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reg appendCrc;
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reg appendCrc;
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reg [5:0] startUppCnt;
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reg [5:0] startUppCnt;
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reg q_start_bit;
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reg q_start_bit;
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//Card initinCMd
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//Card initinCMd
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initial $readmemh("../bin/FLASH.txt",FLASHmem);
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initial $readmemh("../bin/ramdisk2.hex",FLASHmem);
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integer k;
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integer k;
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initial begin
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initial begin
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$display("Contents of Mem after reading data file:");
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$display("Contents of Mem after reading data file:");
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for (k=0; k<10; k=k+1) $display("%d:%h",k,FLASHmem[k]);
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for (k=0; k<512; k=k+1) $display("%d:%h",k,FLASHmem[k]);
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end
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end
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reg qCmd;
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reg qCmd;
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reg [2:0] crcCnt;
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reg [2:0] crcCnt;
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reg add_wrong_cmd_crc;
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reg add_wrong_cmd_crc;
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reg add_wrong_cmd_indx;
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reg add_wrong_cmd_indx;
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reg add_wrong_data_crc;
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reg add_wrong_data_crc;
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initial begin
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initial begin
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add_wrong_data_crc<=0;
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add_wrong_data_crc<=0;
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add_wrong_cmd_indx<=0;
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add_wrong_cmd_indx<=0;
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add_wrong_cmd_crc<=0;
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add_wrong_cmd_crc<=0;
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stop<=1;
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cardIdentificationState<=1;
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cardIdentificationState<=1;
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state<=IDLE;
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state<=IDLE;
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dataState<=DATA_IDLE;
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dataState<=DATA_IDLE;
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Busy<=0;
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Busy<=0;
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oeCmd<=0;
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oeCmd<=0;
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crcCnt<=0;
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crcCnt<=0;
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CardTransferActive<=0;
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CardTransferActive<=0;
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qCmd<=1;
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qCmd<=1;
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oeDat<=0;
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oeDat<=0;
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cmdOut<=0;
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cmdOut<=0;
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cmdWrite<=0;
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cmdWrite<=0;
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InbuffStatus<=0;
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InbuffStatus<=0;
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datOut<=0;
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datOut<=0;
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inCmd<=0;
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inCmd<=0;
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BusWidth<=1;
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BusWidth<=1;
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responseType=0;
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responseType=0;
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mult_read=0;
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mult_write=0;
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crcIn<=0;
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crcIn<=0;
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response_S<=0;
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response_S<=0;
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crcEn<=0;
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crcEn<=0;
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crcRst<=0;
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crcRst<=0;
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cmdRead<=0;
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cmdRead<=0;
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ValidCmd<=0;
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ValidCmd<=0;
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inValidCmd=0;
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inValidCmd=0;
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appendCrc<=0;
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appendCrc<=0;
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RCA<= `RCASTART;
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RCA<= `RCASTART;
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OCR<= `OCRSTART;
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OCR<= `OCRSTART;
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CardStatus <= `STATUSSTART;
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CardStatus <= `STATUSSTART;
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CID<=`CIDSTART;
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CID<=`CIDSTART;
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CSD<=`CSDSTART;
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response_CMD<=0;
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response_CMD<=0;
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outDelayCnt<=0;
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outDelayCnt<=0;
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crcDat_rst<=1;
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crcDat_rst<=1;
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crcDat_en<=0;
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crcDat_en<=0;
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crcDat_in<=0;
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crcDat_in<=0;
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transf_cnt<=0;
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transf_cnt<=0;
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BlockAddr<=0;
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BlockAddr<=0;
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block_cnt <=0;
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block_cnt <=0;
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wptr<=0;
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wptr<=0;
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transf_cnt<=0;
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transf_cnt<=0;
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crcDat_rst<=1;
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crcDat_rst<=1;
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crcDat_en<=0;
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crcDat_en<=0;
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crcDat_in<=0;
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crcDat_in<=0;
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flash_write_cnt<=0;
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flash_write_cnt<=0;
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startUppCnt<=0;
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flash_blockwrite_cnt<=0;
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flash_blockwrite_cnt<=0;
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end
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end
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//CARD logic
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//CARD logic
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always @ (state or cmd or cmdRead or ValidCmd or inValidCmd or cmdWrite or outDelayCnt)
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always @ (state or cmd or cmdRead or ValidCmd or inValidCmd or cmdWrite or outDelayCnt)
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begin : FSM_COMBO
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begin : FSM_COMBO
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next_state = 0;
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next_state = 0;
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case(state)
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case(state)
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IDLE: begin
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IDLE: begin
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if (!cmd)
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if (!cmd)
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next_state = READ_CMD;
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next_state = READ_CMD;
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else
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else
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next_state = IDLE;
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next_state = IDLE;
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end
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end
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READ_CMD: begin
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READ_CMD: begin
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if (cmdRead>= 47)
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if (cmdRead>= 47)
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next_state = ANALYZE_CMD;
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next_state = ANALYZE_CMD;
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else
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else
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next_state = READ_CMD;
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next_state = READ_CMD;
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end
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end
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ANALYZE_CMD: begin
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ANALYZE_CMD: begin
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if ((ValidCmd ) && (outDelayCnt >= `outDelay ))
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if ((ValidCmd ) && (outDelayCnt >= `outDelay ))
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next_state = SEND_CMD;
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next_state = SEND_CMD;
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else if (inValidCmd)
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else if (inValidCmd)
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next_state = IDLE;
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next_state = IDLE;
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else
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else
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next_state = ANALYZE_CMD;
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next_state = ANALYZE_CMD;
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end
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end
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SEND_CMD: begin
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SEND_CMD: begin
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if (cmdWrite>= response_S)
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if (cmdWrite>= response_S)
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next_state = IDLE;
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next_state = IDLE;
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else
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else
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next_state = SEND_CMD;
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next_state = SEND_CMD;
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end
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end
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endcase
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endcase
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end
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end
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always @ (dataState or CardStatus or crc_c or flash_write_cnt or dat[0] )
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always @ (dataState or CardStatus or crc_c or flash_write_cnt or dat[0] )
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begin : FSM_COMBODAT
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begin : FSM_COMBODAT
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next_datastate = 0;
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next_datastate = 0;
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case(dataState)
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case(dataState)
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DATA_IDLE: begin
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DATA_IDLE: begin
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if (CardStatus[12:9]==`RCV )
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if ((CardStatus[12:9]==`RCV) || (mult_write == 1'b1) )
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next_datastate = READ_WAITS;
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next_datastate = READ_WAITS;
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else if (CardStatus[12:9]==`DATAS )
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else if ((CardStatus[12:9]==`DATAS )|| (mult_read == 1'b1) )
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next_datastate = WRITE_DATA;
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next_datastate = WRITE_DATA;
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else
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else
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next_datastate = DATA_IDLE;
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next_datastate = DATA_IDLE;
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end
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end
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READ_WAITS: begin
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READ_WAITS: begin
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if ( dat[0] == 1'b0 )
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if ( dat[0] == 1'b0 )
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next_datastate = READ_DATA;
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next_datastate = READ_DATA;
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else
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else
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next_datastate = READ_WAITS;
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next_datastate = READ_WAITS;
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end
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end
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READ_DATA : begin
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READ_DATA : begin
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if (crc_c==0 )
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if (crc_c==0 )
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next_datastate = WRITE_FLASH;
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next_datastate = WRITE_FLASH;
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else
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else begin
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if (stop == 1'b0)
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next_datastate = READ_DATA;
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next_datastate = READ_DATA;
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else
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next_datastate = DATA_IDLE;
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end
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end
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end
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WRITE_FLASH : begin
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WRITE_FLASH : begin
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if (flash_write_cnt>265 )
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if (flash_write_cnt>265 )
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next_datastate = DATA_IDLE;
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next_datastate = DATA_IDLE;
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else
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else
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next_datastate = WRITE_FLASH;
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next_datastate = WRITE_FLASH;
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end
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end
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WRITE_DATA : begin
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WRITE_DATA : begin
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if (transf_cnt >= `BIT_BLOCK)
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if (transf_cnt >= `BIT_BLOCK)
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next_datastate= DATA_IDLE;
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next_datastate= DATA_IDLE;
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else
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else
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begin
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if (stop == 1'b0)
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next_datastate=WRITE_DATA;
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next_datastate=WRITE_DATA;
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else
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next_datastate = DATA_IDLE;
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end
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end
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end
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endcase
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endcase
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end
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end
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always @ (posedge sdClk )
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always @ (posedge sdClk )
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begin
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begin
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q_start_bit <= dat[0];
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q_start_bit <= dat[0];
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end
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end
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always @ (posedge sdClk )
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always @ (posedge sdClk )
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begin : FSM_SEQ
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begin : FSM_SEQ
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state <= next_state;
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state <= next_state;
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end
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end
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always @ (posedge sdClk )
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always @ (posedge sdClk )
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begin : FSM_SEQDAT
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begin : FSM_SEQDAT
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dataState <= next_datastate;
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dataState <= next_datastate;
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end
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end
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always @ (posedge sdClk) begin
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always @ (posedge sdClk) begin
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if (CardTransferActive) begin
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if (CardTransferActive) begin
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if (InbuffStatus==0) //empty
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if (InbuffStatus==0) //empty
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CardStatus[8]<=1;
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CardStatus[8]<=1;
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else
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else
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CardStatus[8]<=0;
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CardStatus[8]<=0;
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end
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end
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else
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else
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CardStatus[8]<=0;
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CardStatus[8]<=1;
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startUppCnt<=startUppCnt+1;
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startUppCnt<=startUppCnt+1;
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OCR[31]<=Busy;
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OCR[31]<=Busy;
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if (startUppCnt == `TIME_BUSY)
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if (startUppCnt == `TIME_BUSY)
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Busy <=1;
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Busy <=1;
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end
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end
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always @ (posedge sdClk) begin
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always @ (posedge sdClk) begin
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qCmd<=cmd;
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qCmd<=cmd;
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end
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end
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//read data and cmd on rising edge
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//read data and cmd on rising edge
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always @ (posedge sdClk) begin
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always @ (posedge sdClk) begin
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case(state)
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case(state)
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IDLE: begin
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IDLE: begin
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mult_write <= 0;
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mult_read <=0;
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crcIn<=0;
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crcIn<=0;
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crcEn<=0;
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crcEn<=0;
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crcRst<=1;
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crcRst<=1;
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oeCmd<=0;
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oeCmd<=0;
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stop<=0;
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cmdRead<=0;
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cmdRead<=0;
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appendCrc<=0;
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appendCrc<=0;
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ValidCmd<=0;
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ValidCmd<=0;
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inValidCmd=0;
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inValidCmd=0;
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cmdWrite<=0;
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cmdWrite<=0;
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crcCnt<=0;
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crcCnt<=0;
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response_CMD<=0;
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response_CMD<=0;
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response_S<=0;
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response_S<=0;
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outDelayCnt<=0;
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outDelayCnt<=0;
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responseType=0;
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responseType=0;
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end
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end
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READ_CMD: begin //read cmd
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READ_CMD: begin //read cmd
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crcEn<=1;
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crcEn<=1;
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crcRst<=0;
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crcRst<=0;
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crcIn <= #`tIH qCmd;
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crcIn <= #`tIH qCmd;
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inCmd[47-cmdRead] <= #`tIH qCmd;
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inCmd[47-cmdRead] <= #`tIH qCmd;
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cmdRead <= #1 cmdRead+1;
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cmdRead <= #1 cmdRead+1;
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if (cmdRead >= 40)
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if (cmdRead >= 40)
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crcEn<=0;
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crcEn<=0;
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if (cmdRead == 46) begin
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if (cmdRead == 46) begin
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oeCmd<=1;
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oeCmd<=1;
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cmdOut<=1;
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cmdOut<=1;
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end
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end
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end
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end
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ANALYZE_CMD: begin//check for valid cmd
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ANALYZE_CMD: begin//check for valid cmd
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//Wrong CRC go idle
|
//Wrong CRC go idle
|
if (inCmd[46] == 0) //start
|
if (inCmd[46] == 0) //start
|
inValidCmd=1;
|
inValidCmd=1;
|
else if (inCmd[7:1] != crcOut) begin
|
else if (inCmd[7:1] != crcOut) begin
|
inValidCmd=1;
|
inValidCmd=1;
|
$fdisplay(sdModel_file_desc, "**sd_Model Commando CRC Error") ;
|
$fdisplay(sdModel_file_desc, "**sd_Model Commando CRC Error") ;
|
$display(sdModel_file_desc, "**sd_Model Commando CRC Error") ;
|
$display(sdModel_file_desc, "**sd_Model Commando CRC Error") ;
|
end
|
end
|
else if (inCmd[0] != 1) begin//stop
|
else if (inCmd[0] != 1) begin//stop
|
inValidCmd=1;
|
inValidCmd=1;
|
$fdisplay(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;
|
$fdisplay(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;
|
$display(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;
|
$display(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;
|
end
|
end
|
else begin
|
else begin
|
if(outDelayCnt ==0)
|
if(outDelayCnt ==0)
|
CardStatus[3]<=0;
|
CardStatus[3]<=0;
|
case(inCmd[45:40])
|
case(inCmd[45:40])
|
0 : response_S <= 0;
|
0 : response_S <= 0;
|
2 : response_S <= 136;
|
2 : response_S <= 136;
|
3 : response_S <= 48;
|
3 : response_S <= 48;
|
7 : response_S <= 48;
|
7 : response_S <= 48;
|
8 : response_S <= 0;
|
8 : response_S <= 0;
|
|
9 : response_S <= 136;
|
14 : response_S <= 0;
|
14 : response_S <= 0;
|
16 : response_S <= 48;
|
16 : response_S <= 48;
|
17 : response_S <= 48;
|
17 : response_S <= 48;
|
|
18 : response_S <= 48;
|
24 : response_S <= 48;
|
24 : response_S <= 48;
|
|
25 : response_S <= 48;
|
33 : response_S <= 48;
|
33 : response_S <= 48;
|
55 : response_S <= 48;
|
55 : response_S <= 48;
|
41 : response_S <= 48;
|
41 : response_S <= 48;
|
endcase
|
endcase
|
case(inCmd[45:40])
|
case(inCmd[45:40])
|
0 : begin
|
0 : begin
|
response_CMD <= 0;
|
response_CMD <= 0;
|
cardIdentificationState<=1;
|
cardIdentificationState<=1;
|
ResetCard;
|
ResetCard;
|
end
|
end
|
2 : begin
|
2 : begin
|
if (lastCMD != 41 && outDelayCnt==0) begin
|
if (lastCMD != 41 && outDelayCnt==0) begin
|
$fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
|
$fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
|
//$display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
|
//$display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
|
CardStatus[3]<=1;
|
CardStatus[3]<=1;
|
end
|
end
|
response_CMD[127:8] <= CID;
|
response_CMD[127:8] <= CID;
|
appendCrc<=0;
|
appendCrc<=0;
|
CardStatus[12:9] <=2;
|
CardStatus[12:9] <=2;
|
end
|
end
|
3 : begin
|
3 : begin
|
if (lastCMD != 2 && outDelayCnt==0 ) begin
|
if (lastCMD != 2 && outDelayCnt==0 ) begin
|
$fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
|
$fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
|
//$display(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
|
//$display(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
|
CardStatus[3]<=1;
|
CardStatus[3]<=1;
|
end
|
end
|
response_CMD[127:112] <= RCA[15:0] ;
|
response_CMD[127:112] <= RCA[15:0] ;
|
response_CMD[111:96] <= CardStatus[15:0] ;
|
response_CMD[111:96] <= CardStatus[15:0] ;
|
appendCrc<=1;
|
appendCrc<=1;
|
CardStatus[12:9] <=3;
|
CardStatus[12:9] <=3;
|
cardIdentificationState<=0;
|
cardIdentificationState<=0;
|
end
|
end
|
6 : begin
|
6 : begin
|
if (lastCMD == 55 && outDelayCnt==0) begin
|
if (lastCMD == 55 && outDelayCnt==0) begin
|
if (inCmd[9:8] == 2'b10) begin
|
if (inCmd[9:8] == 2'b10) begin
|
BusWidth <=4;
|
BusWidth <=4;
|
$display(sdModel_file_desc, "**BUS WIDTH 4 ") ;
|
$display(sdModel_file_desc, "**BUS WIDTH 4 ") ;
|
end
|
end
|
else
|
else
|
BusWidth <=1;
|
BusWidth <=1;
|
|
|
response_S<=48;
|
response_S<=48;
|
response_CMD[127:96] <= CardStatus;
|
response_CMD[127:96] <= CardStatus;
|
end
|
end
|
else if (outDelayCnt==0)begin
|
else if (outDelayCnt==0)begin
|
response_CMD <= 0;
|
response_CMD <= 0;
|
response_S<=0;
|
response_S<=0;
|
$fdisplay(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;
|
$fdisplay(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;
|
// $display(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;
|
// $display(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;
|
end
|
end
|
end
|
end
|
7: begin
|
7: begin
|
if (outDelayCnt==0) begin
|
if (outDelayCnt==0) begin
|
if (inCmd[39:24]== RCA[15:0]) begin
|
if (inCmd[39:24]== RCA[15:0]) begin
|
CardTransferActive <= 1;
|
CardTransferActive <= 1;
|
response_CMD[127:96] <= CardStatus ;
|
response_CMD[127:96] <= CardStatus ;
|
CardStatus[12:9] <=`TRAN;
|
CardStatus[12:9] <=`TRAN;
|
end
|
end
|
else begin
|
else begin
|
CardTransferActive <= 0;
|
CardTransferActive <= 0;
|
response_CMD[127:96] <= CardStatus ;
|
response_CMD[127:96] <= CardStatus ;
|
CardStatus[12:9] <=3;
|
CardStatus[12:9] <=3;
|
end
|
end
|
end
|
end
|
end
|
end
|
8 : response_CMD[127:96] <= 0; //V1.0 card
|
8 : response_CMD[127:96] <= 0; //V1.0 card
|
|
|
|
9 : begin
|
|
if (lastCMD != 41 && outDelayCnt==0) begin
|
|
$fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
|
|
//$display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
|
|
CardStatus[3]<=1;
|
|
end
|
|
response_CMD[127:8] <= CSD;
|
|
appendCrc<=0;
|
|
CardStatus[12:9] <=2;
|
|
end
|
|
|
|
12: begin
|
|
response_CMD[127:96] <= CardStatus ;
|
|
stop<=1;
|
|
mult_write <= 0;
|
|
mult_read <=0;
|
|
CardStatus[12:9] <= `TRAN;
|
|
end
|
|
|
|
|
16 : begin
|
16 : begin
|
response_CMD[127:96] <= CardStatus ;
|
response_CMD[127:96] <= CardStatus ;
|
|
|
end
|
end
|
|
|
|
|
|
|
|
|
|
|
17 : begin
|
17 : begin
|
if (outDelayCnt==0) begin
|
if (outDelayCnt==0) begin
|
if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
|
if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
|
CardStatus[12:9] <=`DATAS;//Put card in data state
|
CardStatus[12:9] <=`DATAS;//Put card in data state
|
response_CMD[127:96] <= CardStatus ;
|
response_CMD[127:96] <= CardStatus ;
|
BlockAddr = inCmd[39:8];
|
BlockAddr = inCmd[39:8];
|
if (BlockAddr%512 !=0)
|
if (BlockAddr%512 !=0)
|
$display("**Block Misalign Error");
|
$display("**Block Misalign Error");
|
end
|
end
|
else begin
|
else begin
|
response_S <= 0;
|
response_S <= 0;
|
response_CMD[127:96] <= 0;
|
response_CMD[127:96] <= 0;
|
end
|
end
|
end
|
end
|
|
|
end
|
end
|
|
|
|
18 : begin
|
|
if (outDelayCnt==0) begin
|
|
if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
|
|
CardStatus[12:9] <=`DATAS;//Put card in data state
|
|
response_CMD[127:96] <= CardStatus ;
|
|
mult_read <= 1;
|
|
BlockAddr = inCmd[39:8];
|
|
if (BlockAddr%512 !=0)
|
|
$display("**Block Misalign Error");
|
|
end
|
|
else begin
|
|
response_S <= 0;
|
|
response_CMD[127:96] <= 0;
|
|
|
|
end
|
|
end
|
|
|
|
end
|
|
|
24 : begin
|
24 : begin
|
if (outDelayCnt==0) begin
|
if (outDelayCnt==0) begin
|
if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
|
if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
|
if (CardStatus[8]) begin //If Free write buffer
|
if (CardStatus[8]) begin //If Free write buffer
|
CardStatus[12:9] <=`RCV;//Put card in Rcv state
|
CardStatus[12:9] <=`RCV;//Put card in Rcv state
|
response_CMD[127:96] <= CardStatus ;
|
response_CMD[127:96] <= CardStatus ;
|
BlockAddr = inCmd[39:8];
|
BlockAddr = inCmd[39:8];
|
if (BlockAddr%512 !=0)
|
if (BlockAddr%512 !=0)
|
$display("**Block Misalign Error");
|
$display("**Block Misalign Error");
|
end
|
end
|
else begin
|
else begin
|
response_CMD[127:96] <= CardStatus;
|
response_CMD[127:96] <= CardStatus;
|
$fdisplay(sdModel_file_desc, "**Error Try to blockwrite when No Free Writebuffer") ;
|
$fdisplay(sdModel_file_desc, "**Error Try to blockwrite when No Free Writebuffer") ;
|
$display("**Error Try to blockwrite when No Free Writebuffer") ;
|
$display("**Error Try to blockwrite when No Free Writebuffer") ;
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
response_S <= 0;
|
response_S <= 0;
|
response_CMD[127:96] <= 0;
|
response_CMD[127:96] <= 0;
|
end
|
end
|
end
|
end
|
|
|
end
|
end
|
|
25 : begin
|
|
if (outDelayCnt==0) begin
|
|
if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
|
|
if (CardStatus[8]) begin //If Free write buffer
|
|
CardStatus[12:9] <=`RCV;//Put card in Rcv state
|
|
response_CMD[127:96] <= CardStatus ;
|
|
BlockAddr = inCmd[39:8];
|
|
mult_write <= 1;
|
|
if (BlockAddr%512 !=0)
|
|
$display("**Block Misalign Error");
|
|
end
|
|
else begin
|
|
response_CMD[127:96] <= CardStatus;
|
|
$fdisplay(sdModel_file_desc, "**Error Try to blockwrite when No Free Writebuffer") ;
|
|
$display("**Error Try to blockwrite when No Free Writebuffer") ;
|
|
end
|
|
end
|
|
else begin
|
|
response_S <= 0;
|
|
response_CMD[127:96] <= 0;
|
|
end
|
|
end
|
|
end
|
|
|
33 : response_CMD[127:96] <= 48;
|
33 : response_CMD[127:96] <= 48;
|
55 :
|
55 :
|
begin
|
begin
|
response_CMD[127:96] <= CardStatus ;
|
response_CMD[127:96] <= CardStatus ;
|
CardStatus[5] <=1; //Next CMD is AP specific CMD
|
CardStatus[5] <=1; //Next CMD is AP specific CMD
|
appendCrc<=1;
|
appendCrc<=1;
|
end
|
end
|
41 :
|
41 :
|
begin
|
begin
|
if (cardIdentificationState) begin
|
if (cardIdentificationState) begin
|
if (lastCMD != 55 && outDelayCnt==0) begin
|
if (lastCMD != 55 && outDelayCnt==0) begin
|
$fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;
|
$fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;
|
$display( "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;
|
$display( "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;
|
CardStatus[3]<=1;
|
CardStatus[3]<=1;
|
end
|
end
|
else begin
|
else begin
|
responseType=3;
|
responseType=3;
|
response_CMD[127:96] <= OCR;
|
response_CMD[127:96] <= OCR;
|
appendCrc<=0;
|
appendCrc<=0;
|
CardStatus[5] <=0;
|
CardStatus[5] <=0;
|
if (Busy==1)
|
if (Busy==1)
|
CardStatus[12:9] <=1;
|
CardStatus[12:9] <=1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
endcase
|
endcase
|
ValidCmd<=1;
|
ValidCmd<=1;
|
crcIn<=0;
|
crcIn<=0;
|
|
|
outDelayCnt<=outDelayCnt+1;
|
outDelayCnt<=outDelayCnt+1;
|
if (outDelayCnt==`outDelay)
|
if (outDelayCnt==`outDelay)
|
crcRst<=1;
|
crcRst<=1;
|
oeCmd<=1;
|
oeCmd<=1;
|
cmdOut<=1;
|
cmdOut<=1;
|
response_CMD[135:134] <=0;
|
response_CMD[135:134] <=0;
|
|
|
if (responseType != 3)
|
if (responseType != 3)
|
if (!add_wrong_cmd_indx)
|
if (!add_wrong_cmd_indx)
|
response_CMD[133:128] <=inCmd[45:40];
|
response_CMD[133:128] <=inCmd[45:40];
|
else
|
else
|
response_CMD[133:128] <=0;
|
response_CMD[133:128] <=0;
|
|
|
if (responseType == 3)
|
if (responseType == 3)
|
response_CMD[133:128] <=6'b111111;
|
response_CMD[133:128] <=6'b111111;
|
|
|
lastCMD <=inCmd[45:40];
|
lastCMD <=inCmd[45:40];
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
endcase
|
endcase
|
end
|
end
|
|
|
always @ ( negedge sdClk) begin
|
always @ ( negedge sdClk) begin
|
case(state)
|
case(state)
|
|
|
SEND_CMD: begin
|
SEND_CMD: begin
|
crcRst<=0;
|
crcRst<=0;
|
crcEn<=1;
|
crcEn<=1;
|
cmdWrite<=cmdWrite+1;
|
cmdWrite<=cmdWrite+1;
|
if (response_S!=0)
|
if (response_S!=0)
|
cmdOut<=0;
|
cmdOut<=0;
|
else
|
else
|
cmdOut<=1;
|
cmdOut<=1;
|
|
|
if ((cmdWrite>0) && (cmdWrite < response_S-8)) begin
|
if ((cmdWrite>0) && (cmdWrite < response_S-8)) begin
|
cmdOut<=response_CMD[135-cmdWrite];
|
cmdOut<=response_CMD[135-cmdWrite];
|
crcIn<=response_CMD[134-cmdWrite];
|
crcIn<=response_CMD[134-cmdWrite];
|
if (cmdWrite >= response_S-9)
|
if (cmdWrite >= response_S-9)
|
crcEn<=0;
|
crcEn<=0;
|
end
|
end
|
else if (cmdWrite!=0) begin
|
else if (cmdWrite!=0) begin
|
crcEn<=0;
|
crcEn<=0;
|
if (add_wrong_cmd_crc) begin
|
if (add_wrong_cmd_crc) begin
|
cmdOut<=0;
|
cmdOut<=0;
|
crcCnt<=crcCnt+1;
|
crcCnt<=crcCnt+1;
|
end
|
end
|
else begin
|
else begin
|
cmdOut<=crcOut[6-crcCnt];
|
cmdOut<=crcOut[6-crcCnt];
|
crcCnt<=crcCnt+1;
|
crcCnt<=crcCnt+1;
|
if (responseType == 3)
|
if (responseType == 3)
|
cmdOut<=1;
|
cmdOut<=1;
|
end
|
end
|
end
|
end
|
if (cmdWrite == response_S-1)
|
if (cmdWrite == response_S-1)
|
cmdOut<=1;
|
cmdOut<=1;
|
|
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
|
|
integer outdly_cnt;
|
integer outdly_cnt;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
always @ (posedge sdClk) begin
|
always @ (posedge sdClk) begin
|
|
|
case (dataState)
|
case (dataState)
|
DATA_IDLE: begin
|
DATA_IDLE: begin
|
|
|
|
crcDat_rst<=1;
|
|
crcDat_en<=0;
|
|
crcDat_in<=0;
|
|
|
end
|
end
|
|
|
READ_WAITS: begin
|
READ_WAITS: begin
|
oeDat<=0;
|
oeDat<=0;
|
crcDat_rst<=0;
|
crcDat_rst<=0;
|
crcDat_en<=1;
|
crcDat_en<=1;
|
crcDat_in<=0;
|
crcDat_in<=0;
|
crc_c<=15;//
|
crc_c<=15;//
|
crc_ok<=1;
|
crc_ok<=1;
|
end
|
end
|
READ_DATA: begin
|
READ_DATA: begin
|
|
|
|
|
InbuffStatus<=1;
|
InbuffStatus<=1;
|
if (transf_cnt<`BIT_BLOCK_REC) begin
|
if (transf_cnt<`BIT_BLOCK_REC) begin
|
if (wptr)
|
if (wptr)
|
Inbuff[block_cnt][7:4] <= dat;
|
|
else
|
|
Inbuff[block_cnt][3:0] <= dat;
|
Inbuff[block_cnt][3:0] <= dat;
|
|
else
|
|
Inbuff[block_cnt][7:4] <= dat;
|
|
|
if (!add_wrong_data_crc)
|
if (!add_wrong_data_crc)
|
crcDat_in<=dat;
|
crcDat_in<=dat;
|
else
|
else
|
crcDat_in<=4'b1010;
|
crcDat_in<=4'b1010;
|
|
|
crc_ok<=1;
|
crc_ok<=1;
|
transf_cnt<=transf_cnt+1;
|
transf_cnt<=transf_cnt+1;
|
if (wptr)
|
if (wptr)
|
block_cnt<=block_cnt+1;
|
block_cnt<=block_cnt+1;
|
wptr<=~wptr;
|
wptr<=~wptr;
|
|
|
|
|
end
|
end
|
else if ( transf_cnt <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE-1)) begin
|
else if ( transf_cnt <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE-1)) begin
|
transf_cnt<=transf_cnt+1;
|
transf_cnt<=transf_cnt+1;
|
crcDat_en<=0;
|
crcDat_en<=0;
|
last_din <=dat;
|
last_din <=dat;
|
|
|
if (transf_cnt> `BIT_BLOCK_REC) begin
|
if (transf_cnt> `BIT_BLOCK_REC) begin
|
crc_c<=crc_c-1;
|
crc_c<=crc_c-1;
|
|
|
if (crcDat_out[0][crc_c] != last_din[0])
|
if (crcDat_out[0][crc_c] != last_din[0])
|
crc_ok<=0;
|
crc_ok<=0;
|
if (crcDat_out[1][crc_c] != last_din[1])
|
if (crcDat_out[1][crc_c] != last_din[1])
|
crc_ok<=0;
|
crc_ok<=0;
|
if (crcDat_out[2][crc_c] != last_din[2])
|
if (crcDat_out[2][crc_c] != last_din[2])
|
crc_ok<=0;
|
crc_ok<=0;
|
if (crcDat_out[3][crc_c] != last_din[3])
|
if (crcDat_out[3][crc_c] != last_din[3])
|
crc_ok<=0;
|
crc_ok<=0;
|
end
|
end
|
end
|
end
|
end
|
end
|
WRITE_FLASH: begin
|
WRITE_FLASH: begin
|
oeDat<=1;
|
oeDat<=1;
|
block_cnt <=0;
|
block_cnt <=0;
|
wptr<=0;
|
wptr<=0;
|
transf_cnt<=0;
|
transf_cnt<=0;
|
crcDat_rst<=1;
|
crcDat_rst<=1;
|
crcDat_en<=0;
|
crcDat_en<=0;
|
crcDat_in<=0;
|
crcDat_in<=0;
|
|
|
|
|
end
|
end
|
|
|
endcase
|
endcase
|
|
|
|
|
end
|
end
|
|
|
|
|
|
|
reg data_send_index;
|
reg data_send_index;
|
integer write_out_index;
|
integer write_out_index;
|
always @ (negedge sdClk) begin
|
always @ (negedge sdClk) begin
|
|
|
case (dataState)
|
case (dataState)
|
DATA_IDLE: begin
|
DATA_IDLE: begin
|
write_out_index<=0;
|
write_out_index<=0;
|
transf_cnt<=0;
|
transf_cnt<=0;
|
data_send_index<=0;
|
data_send_index<=0;
|
outdly_cnt<=0;
|
outdly_cnt<=0;
|
|
flash_write_cnt<=0;
|
end
|
end
|
|
|
|
|
WRITE_DATA: begin
|
WRITE_DATA: begin
|
oeDat<=1;
|
oeDat<=1;
|
outdly_cnt<=outdly_cnt+1;
|
outdly_cnt<=outdly_cnt+1;
|
|
|
if ( outdly_cnt > `DLY_TO_OUTP) begin
|
if ( outdly_cnt > `DLY_TO_OUTP) begin
|
transf_cnt <= transf_cnt+1;
|
transf_cnt <= transf_cnt+1;
|
crcDat_en<=1;
|
crcDat_en<=1;
|
crcDat_rst<=0;
|
crcDat_rst<=0;
|
|
|
end
|
end
|
else begin
|
else begin
|
crcDat_en<=0;
|
crcDat_en<=0;
|
crcDat_rst<=1;
|
crcDat_rst<=1;
|
oeDat<=1;
|
oeDat<=1;
|
crc_c<=16;
|
crc_c<=16;
|
end
|
end
|
|
|
if (transf_cnt==1) begin
|
if (transf_cnt==1) begin
|
|
|
last_din <= FLASHmem[BlockAddr+(write_out_index)][7:4];
|
last_din <= FLASHmem[BlockAddr+(write_out_index)][7:4];
|
datOut<=0;
|
datOut<=0;
|
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
|
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
|
data_send_index<=1;
|
data_send_index<=1;
|
end
|
end
|
else if ( (transf_cnt>=2) && (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) begin
|
else if ( (transf_cnt>=2) && (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) begin
|
data_send_index<=~data_send_index;
|
data_send_index<=~data_send_index;
|
if (!data_send_index) begin
|
if (!data_send_index) begin
|
last_din<=FLASHmem[BlockAddr+(write_out_index)][7:4];
|
last_din<=FLASHmem[BlockAddr+(write_out_index)][7:4];
|
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
|
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
|
end
|
end
|
else begin
|
else begin
|
last_din<=FLASHmem[BlockAddr+(write_out_index)][3:0];
|
last_din<=FLASHmem[BlockAddr+(write_out_index)][3:0];
|
if (!add_wrong_data_crc)
|
if (!add_wrong_data_crc)
|
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][3:0];
|
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][3:0];
|
else
|
else
|
crcDat_in<=4'b1010;
|
crcDat_in<=4'b1010;
|
write_out_index<=write_out_index+1;
|
write_out_index<=write_out_index+1;
|
|
|
end
|
end
|
|
|
|
|
datOut<= last_din;
|
datOut<= last_din;
|
|
|
|
|
if ( transf_cnt >=`BIT_BLOCK-`CRC_OFF ) begin
|
if ( transf_cnt >=`BIT_BLOCK-`CRC_OFF ) begin
|
crcDat_en<=0;
|
crcDat_en<=0;
|
end
|
end
|
|
|
end
|
end
|
else if (transf_cnt>`BIT_BLOCK-`CRC_OFF & crc_c!=0) begin
|
else if (transf_cnt>`BIT_BLOCK-`CRC_OFF & crc_c!=0) begin
|
datOut<= last_din;
|
datOut<= last_din;
|
crcDat_en<=0;
|
crcDat_en<=0;
|
crc_c<=crc_c-1;
|
crc_c<=crc_c-1;
|
if (crc_c<= 16) begin
|
if (crc_c<= 16) begin
|
datOut[0]<=crcDat_out[0][crc_c-1];
|
datOut[0]<=crcDat_out[0][crc_c-1];
|
datOut[1]<=crcDat_out[1][crc_c-1];
|
datOut[1]<=crcDat_out[1][crc_c-1];
|
datOut[2]<=crcDat_out[2][crc_c-1];
|
datOut[2]<=crcDat_out[2][crc_c-1];
|
datOut[3]<=crcDat_out[3][crc_c-1];
|
datOut[3]<=crcDat_out[3][crc_c-1];
|
end
|
end
|
end
|
end
|
else if (transf_cnt==`BIT_BLOCK-2) begin
|
else if (transf_cnt==`BIT_BLOCK-2) begin
|
datOut<=4'b1111;
|
datOut<=4'b1111;
|
end
|
end
|
else if ((transf_cnt !=0) && (crc_c == 0 ))begin
|
else if ((transf_cnt !=0) && (crc_c == 0 ))begin
|
oeDat<=0;
|
oeDat<=0;
|
CardStatus[12:9] <= `TRAN;
|
CardStatus[12:9] <= `TRAN;
|
end
|
end
|
|
|
|
|
|
|
end
|
end
|
|
|
|
|
|
|
WRITE_FLASH: begin
|
WRITE_FLASH: begin
|
flash_write_cnt<=flash_write_cnt+1;
|
flash_write_cnt<=flash_write_cnt+1;
|
CardStatus[12:9] <= `PRG;
|
CardStatus[12:9] <= `PRG;
|
datOut[0]<=0;
|
datOut[0]<=0;
|
datOut[1]<=1;
|
datOut[1]<=1;
|
datOut[2]<=1;
|
datOut[2]<=1;
|
datOut[3]<=1;
|
datOut[3]<=1;
|
if (flash_write_cnt == 0)
|
if (flash_write_cnt == 0)
|
datOut<=1;
|
datOut<=1;
|
else if(flash_write_cnt == 1)
|
else if(flash_write_cnt == 1)
|
datOut[0]<=1;
|
datOut[0]<=1;
|
else if(flash_write_cnt == 2)
|
else if(flash_write_cnt == 2)
|
datOut[0]<=0;
|
datOut[0]<=0;
|
|
|
|
|
else if ((flash_write_cnt > 2) && (flash_write_cnt < 7)) begin
|
else if ((flash_write_cnt > 2) && (flash_write_cnt < 7)) begin
|
if (crc_ok)
|
if (crc_ok)
|
datOut[0] <=okcrctoken[6-flash_write_cnt];
|
datOut[0] <=okcrctoken[6-flash_write_cnt];
|
else
|
else
|
datOut[0] <= invalidcrctoken[6-flash_write_cnt];
|
datOut[0] <= invalidcrctoken[6-flash_write_cnt];
|
end
|
end
|
else if ((flash_write_cnt >= 7) && (flash_write_cnt < 264)) begin
|
else if ((flash_write_cnt >= 7) && (flash_write_cnt < 264)) begin
|
datOut[0]<=0;
|
datOut[0]<=0;
|
|
|
flash_blockwrite_cnt<=flash_blockwrite_cnt+2;
|
flash_blockwrite_cnt<=flash_blockwrite_cnt+2;
|
FLASHmem[BlockAddr+(flash_blockwrite_cnt)]<=Inbuff[flash_blockwrite_cnt];
|
FLASHmem[BlockAddr+(flash_blockwrite_cnt)]<=Inbuff[flash_blockwrite_cnt];
|
FLASHmem[BlockAddr+(flash_blockwrite_cnt+1)]<=Inbuff[flash_blockwrite_cnt+1];
|
FLASHmem[BlockAddr+(flash_blockwrite_cnt+1)]<=Inbuff[flash_blockwrite_cnt+1];
|
|
|
end
|
end
|
else begin
|
else begin
|
datOut<=1;
|
datOut<=1;
|
InbuffStatus<=0;
|
InbuffStatus<=0;
|
CardStatus[12:9] <= `TRAN;
|
CardStatus[12:9] <= `TRAN;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
integer sdModel_file_desc;
|
integer sdModel_file_desc;
|
|
|
initial
|
initial
|
begin
|
begin
|
sdModel_file_desc = $fopen("../log/sd_model.log");
|
sdModel_file_desc = $fopen("../out/sd_model.log");
|
if (sdModel_file_desc < 2)
|
if (sdModel_file_desc < 2)
|
begin
|
begin
|
$display("*E Could not open/create testbench log file in /log/ directory!");
|
$display("*E Could not open/create testbench log file in /log/ directory!");
|
$finish;
|
$finish;
|
end
|
end
|
end
|
end
|
|
|
task ResetCard; // MAC registers
|
task ResetCard; // MAC registers
|
begin
|
begin
|
add_wrong_data_crc<=0;
|
add_wrong_data_crc<=0;
|
add_wrong_cmd_indx<=0;
|
add_wrong_cmd_indx<=0;
|
add_wrong_cmd_crc<=0;
|
add_wrong_cmd_crc<=0;
|
cardIdentificationState<=1;
|
cardIdentificationState<=1;
|
state<=IDLE;
|
state<=IDLE;
|
dataState<=DATA_IDLE;
|
dataState<=DATA_IDLE;
|
Busy<=0;
|
Busy<=0;
|
oeCmd<=0;
|
oeCmd<=0;
|
crcCnt<=0;
|
crcCnt<=0;
|
CardTransferActive<=0;
|
CardTransferActive<=0;
|
qCmd<=1;
|
qCmd<=1;
|
oeDat<=0;
|
oeDat<=0;
|
cmdOut<=0;
|
cmdOut<=0;
|
cmdWrite<=0;
|
cmdWrite<=0;
|
|
startUppCnt<=0;
|
InbuffStatus<=0;
|
InbuffStatus<=0;
|
datOut<=0;
|
datOut<=0;
|
inCmd<=0;
|
inCmd<=0;
|
BusWidth<=1;
|
BusWidth<=1;
|
responseType=0;
|
responseType=0;
|
crcIn<=0;
|
crcIn<=0;
|
response_S<=0;
|
response_S<=0;
|
crcEn<=0;
|
crcEn<=0;
|
crcRst<=0;
|
crcRst<=0;
|
cmdRead<=0;
|
cmdRead<=0;
|
ValidCmd<=0;
|
ValidCmd<=0;
|
inValidCmd=0;
|
inValidCmd=0;
|
appendCrc<=0;
|
appendCrc<=0;
|
RCA<= `RCASTART;
|
RCA<= `RCASTART;
|
OCR<= `OCRSTART;
|
OCR<= `OCRSTART;
|
CardStatus <= `STATUSSTART;
|
CardStatus <= `STATUSSTART;
|
CID<=`CIDSTART;
|
CID<=`CIDSTART;
|
|
CSD<=`CSDSTART;
|
response_CMD<=0;
|
response_CMD<=0;
|
outDelayCnt<=0;
|
outDelayCnt<=0;
|
crcDat_rst<=1;
|
crcDat_rst<=1;
|
crcDat_en<=0;
|
crcDat_en<=0;
|
crcDat_in<=0;
|
crcDat_in<=0;
|
transf_cnt<=0;
|
transf_cnt<=0;
|
BlockAddr<=0;
|
BlockAddr<=0;
|
block_cnt <=0;
|
block_cnt <=0;
|
wptr<=0;
|
wptr<=0;
|
transf_cnt<=0;
|
transf_cnt<=0;
|
crcDat_rst<=1;
|
crcDat_rst<=1;
|
crcDat_en<=0;
|
crcDat_en<=0;
|
crcDat_in<=0;
|
crcDat_in<=0;
|
flash_write_cnt<=0;
|
flash_write_cnt<=0;
|
flash_blockwrite_cnt<=0;
|
flash_blockwrite_cnt<=0;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
endmodule
|
endmodule
|
|
|
