--Require Modelsim
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--Require Modelsim
|
--Tested on Modelsim 6.5b Revison 2009.05
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--Tested on Modelsim 6.5b Revison 2009.05
|
puts {
|
puts {
|
ModelSimSE SD_HOST_CONTROLLER compile script version 1.1
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ModelSimSE SD_HOST_CONTROLLER compile script version 1.1
|
Copyright (c) Doulos June 2004, SD
|
Copyright (c) Doulos June 2004,
|
|
Modifed 2010, Adam Edvardsson, ORSoC
|
}
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}
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|
|
# Simply change the project settings in this section
|
# Simply change the project settings in this section
|
# for each new project. There should be no need to
|
# for each new project. There should be no need to
|
# modify the rest of the script.
|
# modify the rest of the script.
|
|
|
set library_file_list {
|
set library_file_list {
|
design_library {
|
design_library {
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../../../rtl/sdc_dma/verilog/SD_defines.v
|
../../../rtl/sdc_dma/verilog/sd_defines.v
|
../../../rtl/sdc_dma/verilog/SD_Bd.v
|
../../../rtl/sdc_dma/verilog/sd_bd.v
|
../../../rtl/sdc_dma/verilog/SD_clock_divider.v
|
../../../rtl/sdc_dma/verilog/sd_clock_divider.v
|
../../../rtl/sdc_dma/verilog/SD_cmd_master.v
|
../../../rtl/sdc_dma/verilog/sd_cmd_master.v
|
../../../rtl/sdc_dma/verilog/SD_cmd_serial_host.v
|
../../../rtl/sdc_dma/verilog/sd_cmd_serial_host.v
|
../../../rtl/sdc_dma/verilog/SD_controller_top.v
|
../../../rtl/sdc_dma/verilog/sdc_controller.v
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../../../rtl/sdc_dma/verilog/SD_controller_wb.v
|
../../../rtl/sdc_dma/verilog/sd_controller_wb.v
|
../../../rtl/sdc_dma/verilog/SD_crc_7.v
|
../../../rtl/sdc_dma/verilog/sd_crc_7.v
|
../../../rtl/sdc_dma/verilog/SD_crc_16.v
|
../../../rtl/sdc_dma/verilog/sd_crc_16.v
|
../../../rtl/sdc_dma/verilog/SD_data_host.v
|
../../../rtl/sdc_dma/verilog/sd_data_serial_host.v
|
../../../rtl/sdc_dma/verilog/SD_data_master.v
|
../../../rtl/sdc_dma/verilog/sd_data_master.v
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../../../rtl/sdc_dma/verilog/SD_FIFO_RX_Filler.v
|
../../../rtl/sdc_dma/verilog/sd_fifo_rx_filler.v
|
../../../rtl/sdc_dma/verilog/SD_FIFO_TX_Filler.v
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../../../rtl/sdc_dma/verilog/sd_fifo_tx_filler.v
|
|
|
}
|
}
|
|
|
test_library { ../../../bench/sdc_dma/verilog/wb_model_defines.v
|
test_library { ../../../bench/sdc_dma/verilog/wb_model_defines.v
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../../../bench/sdc_dma/verilog/SD_controller_top_tb.v
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../../../bench/sdc_dma/verilog/sd_controller_top_tb.v
|
../../../bench/sdc_dma/verilog/sdModel.v
|
../../../bench/sdc_dma/verilog/sdModel.v
|
../../../bench/sdc_dma/verilog/timescale.v
|
../../../bench/sdc_dma/verilog/timescale.v
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../../../bench/sdc_dma/verilog/wb_bus_mon.v
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../../../bench/sdc_dma/verilog/wb_bus_mon.v
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../../../bench/sdc_dma/verilog/wb_master32.v
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../../../bench/sdc_dma/verilog/wb_master32.v
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../../../bench/sdc_dma/verilog/wb_master_behavioral.v
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../../../bench/sdc_dma/verilog/wb_master_behavioral.v
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../../../bench/sdc_dma/verilog/wb_slave_behavioral.v
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../../../bench/sdc_dma/verilog/wb_slave_behavioral.v
|
../../../rtl/sdc_dma/verilog/SD_defines.v
|
../../../rtl/sdc_dma/verilog/sd_defines.v
|
../../../rtl/sdc_dma/verilog/SD_Bd.v
|
../../../rtl/sdc_dma/verilog/sd_bd.v
|
../../../rtl/sdc_dma/verilog/SD_clock_divider.v
|
../../../rtl/sdc_dma/verilog/sd_clock_divider.v
|
../../../rtl/sdc_dma/verilog/SD_cmd_master.v
|
../../../rtl/sdc_dma/verilog/sd_cmd_master.v
|
../../../rtl/sdc_dma/verilog/SD_cmd_serial_host.v
|
../../../rtl/sdc_dma/verilog/sd_cmd_serial_host.v
|
../../../rtl/sdc_dma/verilog/SD_controller_top.v
|
../../../rtl/sdc_dma/verilog/sdc_controller.v
|
../../../rtl/sdc_dma/verilog/SD_controller_wb.v
|
../../../rtl/sdc_dma/verilog/sd_controller_wb.v
|
../../../rtl/sdc_dma/verilog/SD_crc_7.v
|
../../../rtl/sdc_dma/verilog/sd_crc_7.v
|
../../../rtl/sdc_dma/verilog/SD_crc_16.v
|
../../../rtl/sdc_dma/verilog/sd_crc_16.v
|
../../../rtl/sdc_dma/verilog/SD_data_host.v
|
../../../rtl/sdc_dma/verilog/sd_data_serial_host.v
|
../../../rtl/sdc_dma/verilog/SD_data_master.v
|
../../../rtl/sdc_dma/verilog/sd_data_master.v
|
../../../rtl/sdc_dma/verilog/SD_FIFO_RX_Filler.v
|
../../../rtl/sdc_dma/verilog/sd_fifo_rx_filler.v
|
../../../rtl/sdc_dma/verilog/SD_FIFO_TX_Filler.v
|
../../../rtl/sdc_dma/verilog/sd_fifo_tx_filler.v
|
../../../rtl/sdc_dma/verilog/fifo/smii_rx_fifo.v
|
../../../rtl/sdc_dma/verilog/sd_rx_fifo.v
|
../../../rtl/sdc_dma/verilog/fifo/smii_tx_fifo.v
|
../../../rtl/sdc_dma/verilog/sd_tx_fifo.v
|
}
|
}
|
}
|
}
|
set top_level test_library.SD_controller_top_tb
|
set top_level test_library.sd_controller_top_tb
|
|
|
|
|
|
|
set wave_patterns {
|
set wave_patterns {
|
/*
|
/*
|
}
|
}
|
set wave_radices {
|
set wave_radices {
|
hexadecimal {data q}
|
hexadecimal {data q}
|
}
|
}
|
|
|
puts {
|
puts {
|
Script commands are:
|
Script commands are:
|
|
|
r = Recompile changed and dependent files
|
r = Recompile changed and dependent files
|
rr = Recompile everything
|
rr = Recompile everything
|
q = Quit without confirmation
|
q = Quit without confirmation
|
}
|
}
|
# After sourcing the script from ModelSim for the
|
# After sourcing the script from ModelSim for the
|
# first time use these commands to recompile.
|
# first time use these commands to recompile.
|
|
|
proc r {} {uplevel #0 source compile.tcl}
|
proc r {} {uplevel #0 source compile.tcl}
|
proc rr {} {global last_compile_time
|
proc rr {} {global last_compile_time
|
set last_compile_time 0
|
set last_compile_time 0
|
r }
|
r }
|
proc q {} {quit -force }
|
proc q {} {quit -force }
|
|
|
#Does this installation support Tk?
|
#Does this installation support Tk?
|
set tk_ok 1
|
set tk_ok 1
|
if [catch {package require Tk}] {set tk_ok 0}
|
if [catch {package require Tk}] {set tk_ok 0}
|
|
|
# Prefer a fixed point font for the transcript
|
# Prefer a fixed point font for the transcript
|
set PrefMain(font) {Courier 10 roman normal}
|
set PrefMain(font) {Courier 10 roman normal}
|
|
|
# Compile out of date files
|
# Compile out of date files
|
set time_now [clock seconds]
|
set time_now [clock seconds]
|
if [catch {set last_compile_time}] {
|
if [catch {set last_compile_time}] {
|
set last_compile_time 0
|
set last_compile_time 0
|
}
|
}
|
foreach {library file_list} $library_file_list {
|
foreach {library file_list} $library_file_list {
|
vlib $library
|
vlib $library
|
vmap work $library
|
vmap work $library
|
foreach file $file_list {
|
foreach file $file_list {
|
if { $last_compile_time < [file mtime $file] } {
|
if { $last_compile_time < [file mtime $file] } {
|
if [regexp {.vhdl?$} $file] {
|
if [regexp {.vhdl?$} $file] {
|
vcom -93 $file
|
vcom -93 $file
|
} else {
|
} else {
|
vlog +incdir+../../../rtl/sdc_dma/verilog/ +incdir+../../../bench/sdc_dma/verilog/ $file
|
vlog +incdir+../../../rtl/sdc_dma/verilog/ +incdir+../../../bench/sdc_dma/verilog/ $file
|
}
|
}
|
set last_compile_time 0
|
set last_compile_time 0
|
}
|
}
|
}
|
}
|
}
|
}
|
set last_compile_time $time_now
|
set last_compile_time $time_now
|
|
|
# Load the simulation
|
# Load the simulation
|
eval vsim $top_level
|
eval vsim $top_level
|
|
|
# If waves are required
|
# If waves are required
|
if [llength $wave_patterns] {
|
if [llength $wave_patterns] {
|
noview wave
|
noview wave
|
foreach pattern $wave_patterns {
|
foreach pattern $wave_patterns {
|
add wave $pattern
|
add wave $pattern
|
}
|
}
|
configure wave -signalnamewidth 1
|
configure wave -signalnamewidth 1
|
foreach {radix signals} $wave_radices {
|
foreach {radix signals} $wave_radices {
|
foreach signal $signals {
|
foreach signal $signals {
|
catch {property wave -radix $radix $signal}
|
catch {property wave -radix $radix $signal}
|
}
|
}
|
}
|
}
|
if $tk_ok {wm geometry .wave [winfo screenwidth .]x330+0-20}
|
# if $tk_ok {wm geometry .wave [winfo screenwidth .]x330+0-20}
|
}
|
}
|
|
|
# Run the simulation
|
# Run the simulation
|
when {/SD_controller_top_tb/succes = 1} {stop}
|
when {/sd_controller_top_tb/succes = 1} {stop}
|
run -all
|
run -all
|
|
|
|
|
# If waves are required
|
# If waves are required
|
if [llength $wave_patterns] {
|
if [llength $wave_patterns] {
|
if $tk_ok {.wave.tree zoomfull}
|
if $tk_ok {.wave.tree zoomfull}
|
}
|
}
|
|
|
|
|
|
|
# How long since project began?
|
# How long since project began?
|
if {[file isfile start_time.txt] == 0} {
|
if {[file isfile start_time.txt] == 0} {
|
set f [open start_time.txt w]
|
set f [open start_time.txt w]
|
puts $f "Start time was [clock seconds]"
|
puts $f "Start time was [clock seconds]"
|
close $f
|
close $f
|
} else {
|
} else {
|
set f [open start_time.txt r]
|
set f [open start_time.txt r]
|
set line [gets $f]
|
set line [gets $f]
|
close $f
|
close $f
|
regexp {\d+} $line start_time
|
regexp {\d+} $line start_time
|
set total_time [expr ([clock seconds]-$start_time)/60]
|
set total_time [expr ([clock seconds]-$start_time)/60]
|
puts "Project time is $total_time minutes"
|
puts "Project time is $total_time minutes"
|
}
|
}
|
|
|
|
|
|
|
