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-- file: SdCmd-ea.vhdl
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-- file: SdCmd-ea.vhdl
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-- author: Rainer Kastl
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-- author: Rainer Kastl
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--
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--
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-- Low level sending commands and receiving responses
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-- Low level sending commands and receiving responses
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-- SD Spec 2.00
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-- SD Spec 2.00
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-------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use ieee.math_real.all;
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use work.Global.all;
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use work.Global.all;
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use work.Sd.all;
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use work.Sd.all;
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use work.CRCs.all;
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use work.CRCs.all;
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entity SdCmd is
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entity SdCmd is
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port (
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port (
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iClk : in std_ulogic; -- Clk, rising edge
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iClk : in std_ulogic; -- Clk, rising edge
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inResetAsync : in std_ulogic; -- Reset, asynchronous active low
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inResetAsync : in std_ulogic; -- Reset, asynchronous active low
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iCmdContent: in aSdCmdContent; -- Content to send to card
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iCmdContent: in aSdCmdContent; -- Content to send to card
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ioCmd : inout std_ulogic -- Cmd line to and from card
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ioCmd : inout std_logic -- Cmd line to and from card
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);
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);
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end entity SdCmd;
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end entity SdCmd;
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architecture Rtl of SdCmd is
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architecture Rtl of SdCmd is
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type aSdCmdState is (idle, startbit, transbit, cmdid, arg, crc, endbit);
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type aSdCmdState is (idle, startbit, transbit, cmdid, arg, crc, endbit);
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signal State, NextState : aSdCmdState;
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signal State, NextState : aSdCmdState;
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signal CrcClear, CrcDataIn : std_ulogic;
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signal CrcClear, CrcDataIn : std_ulogic;
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signal CrcData, SerialCrc : std_ulogic;
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signal CrcData, SerialCrc : std_ulogic;
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signal Counter, NextCounter : unsigned(integer(log2(real(32))) - 1 downto 0);
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signal Counter, NextCounter : unsigned(integer(log2(real(32))) - 1 downto 0);
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begin
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begin
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-- State register
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-- State register
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CmdStateReg : process (iClk, inResetAsync)
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CmdStateReg : process (iClk, inResetAsync)
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begin
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begin
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if inResetAsync = cInactivated then
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if inResetAsync = cInactivated then
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State <= endbit;
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State <= idle;
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Counter <= to_unsigned(0, Counter'length);
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Counter <= to_unsigned(0, Counter'length);
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elsif iClk'event and iClk = cActivated then
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elsif iClk'event and iClk = cActivated then
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State <= NextState;
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State <= NextState;
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Counter <= NextCounter;
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end if;
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end if;
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end process CmdStateReg;
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end process CmdStateReg;
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-- Comb. process
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-- Comb. process
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NextStateAndOutput : process (iCmdContent, State)
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NextStateAndOutput : process (iCmdContent, State, Counter)
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procedure NextStateWhenAllSent (constant length : in natural; constant toState : in aSdCmdState) is
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procedure NextStateWhenAllSent (constant length : in natural; constant toState : in aSdCmdState) is
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begin
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begin
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if (NextCounter < length-1) then
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if (NextCounter < length-1) then
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NextCounter <= NextCounter + 1;
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NextCounter <= NextCounter + 1;
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else
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else
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NextCounter <= to_unsigned(0, NextCounter'length);
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NextCounter <= to_unsigned(0, NextCounter'length);
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NextState <= toState;
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NextState <= toState;
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end if;
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end if;
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end procedure NextStateWhenAllSent;
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end procedure NextStateWhenAllSent;
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procedure SendBitsAndCalcCrc (signal container : in std_ulogic_vector; constant toState : in aSdCmdState) is
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procedure SendBitsAndCalcCrc (signal container : in std_ulogic_vector; constant toState : in aSdCmdState) is
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begin
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begin
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ioCmd <= container(to_integer(NextCounter));
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ioCmd <= container(to_integer(NextCounter));
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CrcData <= container(to_integer(NextCounter));
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CrcData <= container(to_integer(NextCounter));
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CrcDataIn <= cActivated;
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CrcDataIn <= cActivated;
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NextStateWhenAllSent(container'length, toState);
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NextStateWhenAllSent(container'length, toState);
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end procedure SendBitsAndCalcCrc;
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end procedure SendBitsAndCalcCrc;
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begin
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begin
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NextState <= State;
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NextState <= State;
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NextCounter <= Counter;
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NextCounter <= Counter;
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ioCmd <= 'Z';
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ioCmd <= 'Z';
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CrcClear <= cInactivated;
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CrcClear <= cInactivated;
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CrcDataIn <= cInactivated;
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CrcDataIn <= cInactivated;
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CrcData <= cInactivated;
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CrcData <= cInactivated;
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case State is
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case State is
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when idle =>
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when idle =>
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-- todo: implement Sync. with host
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-- todo: implement Sync. with host
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NextState <= startbit;
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NextState <= startbit;
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CrcDataIn <= cActivated;
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CrcData <= cSdStartBit;
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when startbit =>
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when startbit =>
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ioCmd <= cSdStartBit;
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ioCmd <= cSdStartBit;
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NextState <= transbit;
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NextState <= transbit;
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CrcDataIn <= cActivated;
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CrcData <= cSdTransBitHost;
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when transbit =>
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when transbit =>
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ioCmd <= cSdTransBitHost;
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ioCmd <= cSdTransBitHost;
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NextState <= cmdid;
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NextState <= cmdid;
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CrcDataIn <= cActivated;
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CrcData <= iCmdContent.id(to_integer(NextCounter));
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when cmdid =>
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when cmdid =>
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SendBitsAndCalcCrc(iCmdContent.id, arg);
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-- SendBitsAndCalcCrc(iCmdContent.id, arg);
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ioCmd <= iCmdContent.id(to_integer(NextCounter));
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if (NextCounter < iCmdContent.id'length-2) then
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CrcData <= iCmdContent.id(to_integer(NextCounter)+1);
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else
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CrcData <= iCmdContent.arg(0);
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end if;
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CrcDataIn <= cActivated;
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NextStateWhenAllSent(iCmdContent.id'length, arg);
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when arg =>
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when arg =>
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SendBitsAndCalcCrc(iCmdContent.arg, crc);
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-- SendBitsAndCalcCrc(iCmdContent.arg, crc);
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ioCmd <= iCmdContent.arg(to_integer(NextCounter));
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if (NextCounter < iCmdContent.arg'length-2) then
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CrcData <= iCmdContent.arg(to_integer(NextCounter)+1);
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CrcDataIn <= cActivated;
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else
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CrcDataIn <= cInactivated;
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end if;
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NextStateWhenAllSent(iCmdContent.arg'length, crc);
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when crc =>
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when crc =>
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ioCmd <= SerialCrc;
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ioCmd <= SerialCrc;
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NextStateWhenAllSent(crc7'length, endbit);
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NextStateWhenAllSent(crc7'length-1, endbit);
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when endbit =>
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when endbit =>
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ioCmd <= cSdEndBit;
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ioCmd <= cSdEndBit;
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NextState <= idle; -- todo: receive response
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NextState <= idle; -- todo: receive response
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when others =>
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when others =>
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report "SdCmd: State not handled" severity error;
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report "SdCmd: State not handled" severity error;
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end case;
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end case;
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end process NextStateAndOutput;
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end process NextStateAndOutput;
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CRC7_inst: entity work.Crc
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CRC7_inst: entity work.Crc
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generic map(gPolynom => crc7)
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generic map(gPolynom => crc7)
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port map(iClk => iClk,
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port map(iClk => iClk,
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inResetAsync => inResetAsync,
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inResetAsync => inResetAsync,
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iClear => CrcClear,
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iClear => CrcClear,
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iDataIn => CrcDataIn,
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iDataIn => CrcDataIn,
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iData => CrcData,
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iData => CrcData,
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oSerial => SerialCrc);
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oSerial => SerialCrc);
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end architecture Rtl;
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end architecture Rtl;
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