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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [core_SDR_8BIT_complie.log] - Diff between revs 27 and 65
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Rev 65 |
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** Note: (vlog-1901) OptionFile "C:/cygwin/home/Dinesh/projects/sdr_ctrl/sdr_ctrl/trunk/verif/run/vlog.opt" not found. Ignored.
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Model Technology ModelSim ACTEL vlog 6.6d Compiler 2010.11 Nov 2 2010
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Model Technology ModelSim ACTEL vlog 6.6d Compiler 2010.11 Nov 2 2010
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-- Compiling module tb_core
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-- Compiling module tb_core
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-- Compiling module IS42VM16400K
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-- Compiling module IS42VM16400K
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-- Compiling module mt48lc2m32b2
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-- Compiling module mt48lc2m32b2
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-- Compiling module mt48lc8m8a2
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-- Compiling module mt48lc8m8a2
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-- Compiling module sdrc_core
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-- Compiling module sdrc_core
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-- Compiling module sdrc_bank_ctl
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-- Compiling module sdrc_bank_ctl
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-- Compiling module sdrc_bank_fsm
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-- Compiling module sdrc_bank_fsm
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-- Compiling module sdrc_bs_convert
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-- Compiling module sdrc_bs_convert
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-- Compiling module sdrc_req_gen
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-- Compiling module sdrc_req_gen
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-- Compiling module sdrc_xfr_ctl
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-- Compiling module sdrc_xfr_ctl
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Top level modules:
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Top level modules:
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tb_core
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tb_core
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IS42VM16400K
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IS42VM16400K
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mt48lc2m32b2
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mt48lc2m32b2
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