//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the SDRAM Controller project ////
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//// This file is part of the SDRAM Controller project ////
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//// http://www.opencores.org/cores/sdr_ctrl/ ////
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//// http://www.opencores.org/cores/sdr_ctrl/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// SDRAM CTRL definitions. ////
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//// SDRAM CTRL definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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|
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// This testbench verify with SDRAM TOP
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// This testbench verify with SDRAM TOP
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module tb_top;
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module tb_top;
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parameter P_SYS = 10; // 200MHz
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parameter P_SYS = 10; // 200MHz
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parameter P_SDR = 20; // 100MHz
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parameter P_SDR = 20; // 100MHz
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// General
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// General
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reg RESETN;
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reg RESETN;
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reg sdram_clk;
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reg sdram_clk;
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reg sys_clk;
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reg sys_clk;
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|
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initial sys_clk = 0;
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initial sys_clk = 0;
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initial sdram_clk = 0;
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initial sdram_clk = 0;
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|
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always #(P_SYS/2) sys_clk = !sys_clk;
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always #(P_SYS/2) sys_clk = !sys_clk;
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always #(P_SDR/2) sdram_clk = !sdram_clk;
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always #(P_SDR/2) sdram_clk = !sdram_clk;
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|
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parameter dw = 32; // data width
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parameter dw = 32; // data width
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parameter tw = 8; // tag id width
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parameter tw = 8; // tag id width
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parameter bl = 5; // burst_lenght_width
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parameter bl = 5; // burst_lenght_width
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|
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//-------------------------------------------
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//-------------------------------------------
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// WISH BONE Interface
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// WISH BONE Interface
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//-------------------------------------------
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//-------------------------------------------
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//--------------------------------------
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//--------------------------------------
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// Wish Bone Interface
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// Wish Bone Interface
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// -------------------------------------
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// -------------------------------------
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reg wb_stb_i ;
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reg wb_stb_i ;
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wire wb_ack_o ;
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wire wb_ack_o ;
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reg [29:0] wb_addr_i ;
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reg [29:0] wb_addr_i ;
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reg wb_we_i ; // 1 - Write, 0 - Read
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reg wb_we_i ; // 1 - Write, 0 - Read
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reg [dw-1:0] wb_dat_i ;
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reg [dw-1:0] wb_dat_i ;
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reg [dw/8-1:0] wb_sel_i ; // Byte enable
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reg [dw/8-1:0] wb_sel_i ; // Byte enable
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wire [dw-1:0] wb_dat_o ;
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wire [dw-1:0] wb_dat_o ;
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reg wb_cyc_i ;
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reg wb_cyc_i ;
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reg [2:0] wb_cti_i ;
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reg [2:0] wb_cti_i ;
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|
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//--------------------------------------------
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//--------------------------------------------
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// SDRAM I/F
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// SDRAM I/F
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//--------------------------------------------
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//--------------------------------------------
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`ifdef SDR_32BIT
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`ifdef SDR_32BIT
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wire [31:0] Dq ; // SDRAM Read/Write Data Bus
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wire [31:0] Dq ; // SDRAM Read/Write Data Bus
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wire [3:0] sdr_dqm ; // SDRAM DATA Mask
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wire [3:0] sdr_dqm ; // SDRAM DATA Mask
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`elsif SDR_16BIT
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`elsif SDR_16BIT
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wire [15:0] Dq ; // SDRAM Read/Write Data Bus
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wire [15:0] Dq ; // SDRAM Read/Write Data Bus
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wire [1:0] sdr_dqm ; // SDRAM DATA Mask
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wire [1:0] sdr_dqm ; // SDRAM DATA Mask
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`else
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`else
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wire [7:0] Dq ; // SDRAM Read/Write Data Bus
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wire [7:0] Dq ; // SDRAM Read/Write Data Bus
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wire [0:0] sdr_dqm ; // SDRAM DATA Mask
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wire [0:0] sdr_dqm ; // SDRAM DATA Mask
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`endif
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`endif
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wire [1:0] sdr_ba ; // SDRAM Bank Select
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wire [1:0] sdr_ba ; // SDRAM Bank Select
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wire [11:0] sdr_addr ; // SDRAM ADRESS
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wire [11:0] sdr_addr ; // SDRAM ADRESS
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wire sdr_init_done ; // SDRAM Init Done
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wire sdr_init_done ; // SDRAM Init Done
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// to fix the sdram interface timing issue
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// to fix the sdram interface timing issue
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wire #(2.0) sdram_clk_d = sdram_clk;
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wire #(2.0) sdram_clk_d = sdram_clk;
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`ifdef SDR_32BIT
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`ifdef SDR_32BIT
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sdrc_top #(.SDR_DW(32),.SDR_BW(4)) u_dut(
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sdrc_top #(.SDR_DW(32),.SDR_BW(4)) u_dut(
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`elsif SDR_16BIT
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`elsif SDR_16BIT
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sdrc_top #(.SDR_DW(16),.SDR_BW(2)) u_dut(
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sdrc_top #(.SDR_DW(16),.SDR_BW(2)) u_dut(
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`else // 8 BIT SDRAM
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`else // 8 BIT SDRAM
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sdrc_top #(.SDR_DW(8),.SDR_BW(1)) u_dut(
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sdrc_top #(.SDR_DW(8),.SDR_BW(1)) u_dut(
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`endif
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`endif
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// System
|
// System
|
`ifdef SDR_32BIT
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`ifdef SDR_32BIT
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.sdr_width (2'b00 ), // 32 BIT SDRAM
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.cfg_sdr_width (2'b00 ), // 32 BIT SDRAM
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`elsif SDR_16BIT
|
`elsif SDR_16BIT
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.sdr_width (2'b01 ), // 16 BIT SDRAM
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.cfg_sdr_width (2'b01 ), // 16 BIT SDRAM
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`else
|
`else
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.sdr_width (2'b10 ), // 8 BIT SDRAM
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.cfg_sdr_width (2'b10 ), // 8 BIT SDRAM
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`endif
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`endif
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.cfg_colbits (2'b00 ), // 8 Bit Column Address
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.cfg_colbits (2'b00 ), // 8 Bit Column Address
|
|
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/* WISH BONE */
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/* WISH BONE */
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.wb_rst_i (!RESETN ),
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.wb_rst_i (!RESETN ),
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.wb_clk_i (sys_clk ),
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.wb_clk_i (sys_clk ),
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|
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.wb_stb_i (wb_stb_i ),
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.wb_stb_i (wb_stb_i ),
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.wb_ack_o (wb_ack_o ),
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.wb_ack_o (wb_ack_o ),
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.wb_addr_i (wb_addr_i ),
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.wb_addr_i (wb_addr_i ),
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.wb_we_i (wb_we_i ),
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.wb_we_i (wb_we_i ),
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.wb_dat_i (wb_dat_i ),
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.wb_dat_i (wb_dat_i ),
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.wb_sel_i (wb_sel_i ),
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.wb_sel_i (wb_sel_i ),
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.wb_dat_o (wb_dat_o ),
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.wb_dat_o (wb_dat_o ),
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.wb_cyc_i (wb_cyc_i ),
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.wb_cyc_i (wb_cyc_i ),
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.wb_cti_i (wb_cti_i ),
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.wb_cti_i (wb_cti_i ),
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|
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/* Interface to SDRAMs */
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/* Interface to SDRAMs */
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.sdram_clk (sdram_clk ),
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.sdram_clk (sdram_clk ),
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.sdram_resetn (RESETN ),
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.sdram_resetn (RESETN ),
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.sdr_cs_n (sdr_cs_n ),
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.sdr_cs_n (sdr_cs_n ),
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.sdr_cke (sdr_cke ),
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.sdr_cke (sdr_cke ),
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.sdr_ras_n (sdr_ras_n ),
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.sdr_ras_n (sdr_ras_n ),
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.sdr_cas_n (sdr_cas_n ),
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.sdr_cas_n (sdr_cas_n ),
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.sdr_we_n (sdr_we_n ),
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.sdr_we_n (sdr_we_n ),
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.sdr_dqm (sdr_dqm ),
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.sdr_dqm (sdr_dqm ),
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.sdr_ba (sdr_ba ),
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.sdr_ba (sdr_ba ),
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.sdr_addr (sdr_addr ),
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.sdr_addr (sdr_addr ),
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.sdr_dq (Dq ),
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.sdr_dq (Dq ),
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|
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/* Parameters */
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/* Parameters */
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.sdr_init_done (sdr_init_done ),
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.sdr_init_done (sdr_init_done ),
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.cfg_req_depth (2'h2 ), //how many req. buffer should hold
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.cfg_req_depth (2'h2 ), //how many req. buffer should hold
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.cfg_sdr_en (1'b1 ),
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.cfg_sdr_en (1'b1 ),
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.cfg_sdr_mode_reg (12'h033 ),
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.cfg_sdr_mode_reg (12'h033 ),
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.cfg_sdr_tras_d (4'h4 ),
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.cfg_sdr_tras_d (4'h4 ),
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.cfg_sdr_trp_d (4'h2 ),
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.cfg_sdr_trp_d (4'h2 ),
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.cfg_sdr_trcd_d (4'h2 ),
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.cfg_sdr_trcd_d (4'h2 ),
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.cfg_sdr_cas (3'h3 ),
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.cfg_sdr_cas (3'h3 ),
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.cfg_sdr_trcar_d (4'h7 ),
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.cfg_sdr_trcar_d (4'h7 ),
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.cfg_sdr_twr_d (4'h1 ),
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.cfg_sdr_twr_d (4'h1 ),
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.cfg_sdr_rfsh (12'hC35 ),
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.cfg_sdr_rfsh (12'hC35 ),
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.cfg_sdr_rfmax (3'h6 )
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.cfg_sdr_rfmax (3'h6 )
|
|
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);
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);
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`ifdef SDR_32BIT
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`ifdef SDR_32BIT
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mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
|
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
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.Dq (Dq ) ,
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.Dq (Dq ) ,
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.Addr (sdr_addr ),
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.Addr (sdr_addr ),
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.Ba (sdr_ba ),
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.Ba (sdr_ba ),
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.Clk (sdram_clk_d ),
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.Clk (sdram_clk_d ),
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.Cke (sdr_cke ),
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.Cke (sdr_cke ),
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.Cs_n (sdr_cs_n ),
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.Cs_n (sdr_cs_n ),
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.Ras_n (sdr_ras_n ),
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.Ras_n (sdr_ras_n ),
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.Cas_n (sdr_cas_n ),
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.Cas_n (sdr_cas_n ),
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.We_n (sdr_we_n ),
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.We_n (sdr_we_n ),
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.Dqm (sdr_dqm )
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.Dqm (sdr_dqm )
|
);
|
);
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|
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`elsif SDR_16BIT
|
`elsif SDR_16BIT
|
|
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IS42VM16400K u_sdram16 (
|
IS42VM16400K u_sdram16 (
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.dq (Dq ),
|
.dq (Dq ),
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.addr (sdr_addr ),
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.addr (sdr_addr ),
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.ba (sdr_ba ),
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.ba (sdr_ba ),
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.clk (sdram_clk_d ),
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.clk (sdram_clk_d ),
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.cke (sdr_cke ),
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.cke (sdr_cke ),
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.csb (sdr_cs_n ),
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.csb (sdr_cs_n ),
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.rasb (sdr_ras_n ),
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.rasb (sdr_ras_n ),
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.casb (sdr_cas_n ),
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.casb (sdr_cas_n ),
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.web (sdr_we_n ),
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.web (sdr_we_n ),
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.dqm (sdr_dqm )
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.dqm (sdr_dqm )
|
);
|
);
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`else
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`else
|
|
|
|
|
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
|
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
|
.Dq (Dq ) ,
|
.Dq (Dq ) ,
|
.Addr (sdr_addr ),
|
.Addr (sdr_addr ),
|
.Ba (sdr_ba ),
|
.Ba (sdr_ba ),
|
.Clk (sdram_clk_d ),
|
.Clk (sdram_clk_d ),
|
.Cke (sdr_cke ),
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.Cke (sdr_cke ),
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.Cs_n (sdr_cs_n ),
|
.Cs_n (sdr_cs_n ),
|
.Ras_n (sdr_ras_n ),
|
.Ras_n (sdr_ras_n ),
|
.Cas_n (sdr_cas_n ),
|
.Cas_n (sdr_cas_n ),
|
.We_n (sdr_we_n ),
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.We_n (sdr_we_n ),
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.Dqm (sdr_dqm )
|
.Dqm (sdr_dqm )
|
);
|
);
|
`endif
|
`endif
|
|
|
//--------------------
|
//--------------------
|
// Write/Read Burst FIFO
|
// Write/Read Burst FIFO
|
//--------------------
|
//--------------------
|
int wrdfifo[$]; // write data fifo
|
int wrdfifo[$]; // write data fifo
|
int rddfifo[$]; // read data fifo
|
int rddfifo[$]; // read data fifo
|
|
|
reg [31:0] read_data;
|
reg [31:0] read_data;
|
reg [31:0] ErrCnt;
|
reg [31:0] ErrCnt;
|
int k;
|
int k;
|
reg [31:0] StartAddr;
|
reg [31:0] StartAddr;
|
/////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////
|
// Test Case
|
// Test Case
|
/////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////
|
|
|
initial begin //{
|
initial begin //{
|
ErrCnt = 0;
|
ErrCnt = 0;
|
wb_addr_i = 0;
|
wb_addr_i = 0;
|
wb_dat_i = 0;
|
wb_dat_i = 0;
|
wb_sel_i = 4'h0;
|
wb_sel_i = 4'h0;
|
wb_we_i = 0;
|
wb_we_i = 0;
|
wb_stb_i = 0;
|
wb_stb_i = 0;
|
wb_cyc_i = 0;
|
wb_cyc_i = 0;
|
|
|
RESETN = 1'h1;
|
RESETN = 1'h1;
|
|
|
#100
|
#100
|
// Applying reset
|
// Applying reset
|
RESETN = 1'h0;
|
RESETN = 1'h0;
|
#10000;
|
#10000;
|
// Releasing reset
|
// Releasing reset
|
RESETN = 1'h1;
|
RESETN = 1'h1;
|
#1000;
|
#1000;
|
wait(u_dut.sdr_init_done == 1);
|
wait(u_dut.sdr_init_done == 1);
|
|
|
#1000;
|
#1000;
|
|
|
wrdfifo.push_back(32'h11223344);
|
wrdfifo.push_back(32'h11223344);
|
wrdfifo.push_back(32'h22334455);
|
wrdfifo.push_back(32'h22334455);
|
wrdfifo.push_back(32'h33445566);
|
wrdfifo.push_back(32'h33445566);
|
wrdfifo.push_back(32'h44556677);
|
wrdfifo.push_back(32'h44556677);
|
wrdfifo.push_back(32'h55667788);
|
wrdfifo.push_back(32'h55667788);
|
|
|
burst_write(32'h40000);
|
burst_write(32'h40000);
|
#1000;
|
#1000;
|
burst_read(32'h40000);
|
burst_read(32'h40000);
|
|
|
#1000;
|
#1000;
|
burst_write(32'h7000_0000);
|
burst_write(32'h7000_0000);
|
#1000;
|
#1000;
|
burst_read(32'h7000_0000);
|
burst_read(32'h7000_0000);
|
|
|
for(k=0; k < 20; k++) begin
|
for(k=0; k < 20; k++) begin
|
StartAddr = $random & 32'h07FFFFFF;
|
StartAddr = $random & 32'h07FFFFFF;
|
burst_write(StartAddr);
|
burst_write(StartAddr);
|
#1000;
|
#1000;
|
burst_read(StartAddr);
|
burst_read(StartAddr);
|
end
|
end
|
|
|
|
|
#10000;
|
#10000;
|
|
|
$display("###############################");
|
$display("###############################");
|
if(ErrCnt == 0)
|
if(ErrCnt == 0)
|
$display("STATUS: SDRAM Write/Read TEST PASSED");
|
$display("STATUS: SDRAM Write/Read TEST PASSED");
|
else
|
else
|
$display("ERROR: SDRAM Write/Read TEST FAILED");
|
$display("ERROR: SDRAM Write/Read TEST FAILED");
|
$display("###############################");
|
$display("###############################");
|
|
|
$finish;
|
$finish;
|
end
|
end
|
|
|
task burst_write;
|
task burst_write;
|
input [31:0] Address;
|
input [31:0] Address;
|
int i;
|
int i;
|
begin
|
begin
|
@ (negedge sys_clk);
|
@ (negedge sys_clk);
|
$display("Write Address: %x, Burst Size: %d",Address,wrdfifo.size);
|
$display("Write Address: %x, Burst Size: %d",Address,wrdfifo.size);
|
|
|
for(i=0; i < wrdfifo.size; i++) begin
|
for(i=0; i < wrdfifo.size; i++) begin
|
wb_stb_i = 1;
|
wb_stb_i = 1;
|
wb_cyc_i = 1;
|
wb_cyc_i = 1;
|
wb_we_i = 1;
|
wb_we_i = 1;
|
wb_sel_i = 4'b1111;
|
wb_sel_i = 4'b1111;
|
wb_addr_i = Address[31:2]+i;
|
wb_addr_i = Address[31:2]+i;
|
wb_dat_i = wrdfifo[i];
|
wb_dat_i = wrdfifo[i];
|
|
|
do begin
|
do begin
|
@ (posedge sys_clk);
|
@ (posedge sys_clk);
|
end while(wb_ack_o == 1'b0);
|
end while(wb_ack_o == 1'b0);
|
@ (negedge sys_clk);
|
@ (negedge sys_clk);
|
|
|
$display("Status: Burst-No: %d Write Address: %x WriteData: %x ",i,wb_addr_i,wb_dat_i);
|
$display("Status: Burst-No: %d Write Address: %x WriteData: %x ",i,wb_addr_i,wb_dat_i);
|
end
|
end
|
wb_stb_i = 0;
|
wb_stb_i = 0;
|
wb_cyc_i = 0;
|
wb_cyc_i = 0;
|
end
|
end
|
endtask
|
endtask
|
|
|
task burst_read;
|
task burst_read;
|
input [31:0] Address;
|
input [31:0] Address;
|
|
|
int i,j;
|
int i,j;
|
reg [31:0] rd_data;
|
reg [31:0] rd_data;
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begin
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begin
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@ (negedge sys_clk);
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@ (negedge sys_clk);
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|
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for(j=0; j < wrdfifo.size; j++) begin
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for(j=0; j < wrdfifo.size; j++) begin
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wb_stb_i = 1;
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wb_stb_i = 1;
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wb_cyc_i = 1;
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wb_cyc_i = 1;
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wb_we_i = 0;
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wb_we_i = 0;
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wb_addr_i = Address[31:2]+j;
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wb_addr_i = Address[31:2]+j;
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|
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do begin
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do begin
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@ (posedge sys_clk);
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@ (posedge sys_clk);
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end while(wb_ack_o == 1'b0);
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end while(wb_ack_o == 1'b0);
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if(wb_dat_o !== wrdfifo[j]) begin
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if(wb_dat_o !== wrdfifo[j]) begin
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$display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,wb_addr_i,wb_dat_o,wrdfifo[j]);
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$display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,wb_addr_i,wb_dat_o,wrdfifo[j]);
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ErrCnt = ErrCnt+1;
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ErrCnt = ErrCnt+1;
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end else begin
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end else begin
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$display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,wb_addr_i,wb_dat_o);
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$display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,wb_addr_i,wb_dat_o);
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end
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end
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@ (negedge sdram_clk);
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@ (negedge sdram_clk);
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end
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end
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wb_stb_i = 0;
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wb_stb_i = 0;
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wb_cyc_i = 0;
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wb_cyc_i = 0;
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end
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end
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endtask
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endtask
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|
|
|
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endmodule
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endmodule
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|
|
