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----------------------------------------------------------------------------------
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-- Company: OPL Aerospatiale AG
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-- Company: OPL Aerospatiale AG
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-- Engineer: Owen Lynn <lynn0p@hotmail.com>
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-- Engineer: Owen Lynn <lynn0p@hotmail.com>
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--
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--
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-- Create Date: 13:08:21 08/30/2009
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-- Create Date: 13:08:21 08/30/2009
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-- Design Name:
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-- Design Name:
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-- Module Name: sdram_writer - impl
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-- Module Name: sdram_writer - impl
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description: This module is responsible for generating the dqs, dq and dm waveforms
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-- Description: This module is responsible for generating the dqs, dq and dm waveforms
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-- needed to tell the chip what to store.
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-- needed to tell the chip what to store.
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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-- Copyright (c) 2009 Owen Lynn <lynn0p@hotmail.com>
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-- Copyright (c) 2009 Owen Lynn <lynn0p@hotmail.com>
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-- Released under the GNU Lesser General Public License, Version 3
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-- Released under the GNU Lesser General Public License, Version 3
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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-- Uses ODDR2 registers to generate the required DDR signals. Don't have to be as careful with the
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-- Uses ODDR2 registers to generate the required DDR signals. Don't have to be as
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-- timings as with sdram_reader, but you need to be able to feed the ODDR2's within their setup
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-- careful with the timings as with sdram_reader, but you need to be able to feed
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-- and hold windows. Or very very hilarious things will occur. Post-PAR simulation is good for
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-- the ODDR2's within their setup and hold windows. Or very very hilarious things
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-- getting a feel for the (mis)timings.
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-- will occur. Post-PAR simulation is good for getting a feel for the
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-- (mis)timings.
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entity sdram_writer is
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entity sdram_writer is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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clk090 : in std_logic;
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clk090 : in std_logic;
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clk180 : in std_logic;
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clk180 : in std_logic;
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clk270 : in std_logic;
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clk270 : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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addr : in std_logic;
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addr : in std_logic;
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data_o : in std_logic_vector(7 downto 0);
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data_o : in std_logic_vector(7 downto 0);
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dqs : out std_logic_vector(1 downto 0);
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dqs : out std_logic_vector(1 downto 0);
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dm : out std_logic_vector(1 downto 0);
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dm : out std_logic_vector(1 downto 0);
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dq : out std_logic_vector(15 downto 0)
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dq : out std_logic_vector(15 downto 0)
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);
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);
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end sdram_writer;
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end sdram_writer;
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architecture impl of sdram_writer is
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architecture impl of sdram_writer is
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component oddr2_2 is
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component oddr2_2 is
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port(
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port(
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Q : out std_logic_vector(1 downto 0);
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Q : out std_logic_vector(1 downto 0);
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C0 : in std_logic;
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C0 : in std_logic;
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C1 : in std_logic;
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C1 : in std_logic;
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CE : in std_logic;
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CE : in std_logic;
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D0 : in std_logic_vector(1 downto 0);
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D0 : in std_logic_vector(1 downto 0);
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D1 : in std_logic_vector(1 downto 0);
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D1 : in std_logic_vector(1 downto 0);
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R : in std_logic;
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R : in std_logic;
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S : in std_logic );
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S : in std_logic );
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end component;
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end component;
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component oddr2_16 is
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component oddr2_16 is
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port(
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port(
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Q : out std_logic_vector(15 downto 0);
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Q : out std_logic_vector(15 downto 0);
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C0 : in std_logic;
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C0 : in std_logic;
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C1 : in std_logic;
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C1 : in std_logic;
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CE : in std_logic;
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CE : in std_logic;
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D0 : in std_logic_vector(15 downto 0);
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D0 : in std_logic_vector(15 downto 0);
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D1 : in std_logic_vector(15 downto 0);
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D1 : in std_logic_vector(15 downto 0);
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R : in std_logic;
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R : in std_logic;
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S : in std_logic );
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S : in std_logic );
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end component;
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end component;
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type WRITER_DQS_STATES is ( STATE_WRITER_DQS_0, STATE_WRITER_DQS_1, STATE_WRITER_DQS_DONE );
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type WRITER_DQS_STATES is ( STATE_WRITER_DQS_0, STATE_WRITER_DQS_1, STATE_WRITER_DQS_DONE );
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type WRITER_DM_STATES is ( STATE_WRITER_DM_0, STATE_WRITER_DM_1, STATE_WRITER_DM_DONE );
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type WRITER_DM_STATES is ( STATE_WRITER_DM_0, STATE_WRITER_DM_1, STATE_WRITER_DM_DONE );
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signal writer_dqs_state : WRITER_DQS_STATES := STATE_WRITER_DQS_0;
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signal writer_dqs_state : WRITER_DQS_STATES := STATE_WRITER_DQS_0;
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signal writer_dm_state : WRITER_DM_STATES := STATE_WRITER_DM_0;
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signal writer_dm_state : WRITER_DM_STATES := STATE_WRITER_DM_0;
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signal dqs_rising : std_logic_vector(1 downto 0) := "00";
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signal dqs_rising : std_logic_vector(1 downto 0) := "00";
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signal dqs_falling : std_logic_vector(1 downto 0) := "00";
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signal dqs_falling : std_logic_vector(1 downto 0) := "00";
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signal dqs_fsm_r : std_logic;
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signal dqs_fsm_r : std_logic;
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signal dqs_fsm_f : std_logic;
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signal dqs_fsm_f : std_logic;
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signal dm_rising : std_logic_vector(1 downto 0) := "11";
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signal dm_rising : std_logic_vector(1 downto 0) := "11";
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signal dm_falling : std_logic_vector(1 downto 0) := "11";
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signal dm_falling : std_logic_vector(1 downto 0) := "11";
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signal dq_rising : std_logic_vector(15 downto 0) := x"0000";
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signal dq_rising : std_logic_vector(15 downto 0) := x"0000";
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signal dq_falling : std_logic_vector(15 downto 0) := x"0000";
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signal dq_falling : std_logic_vector(15 downto 0) := x"0000";
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signal data_out : std_logic_vector(15 downto 0);
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signal data_out : std_logic_vector(15 downto 0);
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signal mask_out : std_logic_vector(1 downto 0);
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signal mask_out : std_logic_vector(1 downto 0);
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begin
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begin
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ODDR2_dqs: oddr2_2
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ODDR2_dqs: oddr2_2
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port map(
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port map(
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Q => dqs,
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Q => dqs,
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C0 => clk,
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C0 => clk,
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C1 => clk180,
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C1 => clk180,
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CE => '1',
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CE => '1',
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D0 => dqs_rising,
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D0 => dqs_rising,
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D1 => dqs_falling,
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D1 => dqs_falling,
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R => '0',
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R => '0',
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S => '0'
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S => '0'
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);
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);
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ODDR2_dm: oddr2_2
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ODDR2_dm: oddr2_2
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port map(
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port map(
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Q => dm,
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Q => dm,
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C0 => clk090,
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C0 => clk090,
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C1 => clk270,
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C1 => clk270,
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CE => '1',
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CE => '1',
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D0 => dm_rising,
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D0 => dm_rising,
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D1 => dm_falling,
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D1 => dm_falling,
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R => '0',
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R => '0',
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S => '0'
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S => '0'
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);
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);
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ODDR2_dq: oddr2_16
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ODDR2_dq: oddr2_16
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port map(
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port map(
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Q => dq,
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Q => dq,
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C0 => clk090,
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C0 => clk090,
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C1 => clk270,
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C1 => clk270,
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CE => '1',
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CE => '1',
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D0 => dq_rising,
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D0 => dq_rising,
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D1 => dq_falling,
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D1 => dq_falling,
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R => '0',
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R => '0',
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S => '0'
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S => '0'
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);
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);
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dqs_rising(0) <= dqs_fsm_r;
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dqs_rising(0) <= dqs_fsm_r;
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dqs_rising(1) <= dqs_fsm_r;
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dqs_rising(1) <= dqs_fsm_r;
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dqs_falling(0) <= dqs_fsm_f;
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dqs_falling(0) <= dqs_fsm_f;
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dqs_falling(1) <= dqs_fsm_f;
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dqs_falling(1) <= dqs_fsm_f;
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-- this drives the oddr2_dqs
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-- this drives the oddr2_dqs
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process (clk180,rst)
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process (clk180,rst)
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begin
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begin
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if (rst = '1') then
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if (rst = '1') then
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dqs_fsm_r <= '0';
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dqs_fsm_r <= '0';
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dqs_fsm_f <= '0';
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dqs_fsm_f <= '0';
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writer_dqs_state <= STATE_WRITER_DQS_0;
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writer_dqs_state <= STATE_WRITER_DQS_0;
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elsif (rising_edge(clk180)) then
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elsif (rising_edge(clk180)) then
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case writer_dqs_state is
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case writer_dqs_state is
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when STATE_WRITER_DQS_0 =>
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when STATE_WRITER_DQS_0 =>
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dqs_fsm_r <= '0';
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dqs_fsm_r <= '0';
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dqs_fsm_f <= '0';
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dqs_fsm_f <= '0';
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writer_dqs_state <= STATE_WRITER_DQS_1;
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writer_dqs_state <= STATE_WRITER_DQS_1;
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when STATE_WRITER_DQS_1 =>
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when STATE_WRITER_DQS_1 =>
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dqs_fsm_r <= '1';
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dqs_fsm_r <= '1';
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dqs_fsm_f <= '0';
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dqs_fsm_f <= '0';
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writer_dqs_state <= STATE_WRITER_DQS_DONE;
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writer_dqs_state <= STATE_WRITER_DQS_DONE;
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when STATE_WRITER_DQS_DONE =>
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when STATE_WRITER_DQS_DONE =>
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dqs_fsm_r <= '0';
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dqs_fsm_r <= '0';
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dqs_fsm_f <= '0';
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dqs_fsm_f <= '0';
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writer_dqs_state <= STATE_WRITER_DQS_DONE;
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writer_dqs_state <= STATE_WRITER_DQS_DONE;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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data_out <= (x"00" & data_o) when addr = '0' else (data_o & x"00");
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data_out <= (x"00" & data_o) when addr = '0' else (data_o & x"00");
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mask_out <= "10" when addr = '0' else "01";
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mask_out <= "10" when addr = '0' else "01";
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-- this drives the oddr2_dm and oddr2_dq
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-- this drives the oddr2_dm and oddr2_dq
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process(clk,rst)
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process(clk,rst)
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begin
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begin
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if (rst = '1') then
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if (rst = '1') then
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dm_rising <= "11";
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dm_rising <= "11";
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dq_rising <= x"0000";
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dq_rising <= x"0000";
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dm_falling <= "11";
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dm_falling <= "11";
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dq_falling <= x"0000";
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dq_falling <= x"0000";
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writer_dm_state <= STATE_WRITER_DM_0;
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writer_dm_state <= STATE_WRITER_DM_0;
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elsif (rising_edge(clk)) then
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elsif (rising_edge(clk)) then
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case writer_dm_state is
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case writer_dm_state is
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when STATE_WRITER_DM_0 =>
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when STATE_WRITER_DM_0 =>
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dm_rising <= "11";
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dm_rising <= "11";
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dq_rising <= x"0000";
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dq_rising <= x"0000";
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dm_falling <= mask_out;
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dm_falling <= mask_out;
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dq_falling <= data_out;
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dq_falling <= data_out;
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writer_dm_state <= STATE_WRITER_DM_1;
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writer_dm_state <= STATE_WRITER_DM_1;
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when STATE_WRITER_DM_1 =>
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when STATE_WRITER_DM_1 =>
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dm_rising <= "11";
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dm_rising <= "11";
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dq_rising <= x"0000";
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dq_rising <= x"0000";
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dm_falling <= "11";
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dm_falling <= "11";
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dq_falling <= x"0000";
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dq_falling <= x"0000";
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writer_dm_state <= STATE_WRITER_DM_DONE;
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writer_dm_state <= STATE_WRITER_DM_DONE;
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when STATE_WRITER_DM_DONE =>
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when STATE_WRITER_DM_DONE =>
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dm_rising <= "00";
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dm_rising <= "00";
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dm_falling <= "00";
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dm_falling <= "00";
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writer_dm_state <= STATE_WRITER_DM_DONE;
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writer_dm_state <= STATE_WRITER_DM_DONE;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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end impl;
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end impl;
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