// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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//
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//
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// Revision Control Information
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// Revision Control Information
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//
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//
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// $RCSfile: ethmon_32.v,v $
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// $RCSfile: ethmon_32.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/mon/ethmon_32.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/mon/ethmon_32.v,v $
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//
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//
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// $Revision: #1 $
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// $Revision: #1 $
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// $Date: 2011/11/10 $
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// $Date: 2012/06/21 $
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// Check in by : $Author: max $
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// Check in by : $Author: swbranch $
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// Author : SKNg/TTChong
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// Author : SKNg/TTChong
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//
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//
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// Project : Triple Speed Ethernet - 10/100/1000 MAC
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// Project : Triple Speed Ethernet - 10/100/1000 MAC
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//
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//
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// Description : (Simulation only)
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// Description : (Simulation only)
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//
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//
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// Ethernet Traffic Monitor/Decoder for 32 bit MAC Atlantic client interface
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// Ethernet Traffic Monitor/Decoder for 32 bit MAC Atlantic client interface
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// Instantiated in top_ethmonitor32 (top_ethmon32.v)
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// Instantiated in top_ethmonitor32 (top_ethmon32.v)
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//
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//
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//
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//
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// ALTERA Confidential and Proprietary
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// ALTERA Confidential and Proprietary
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// Copyright 2006 (c) Altera Corporation
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// Copyright 2006 (c) Altera Corporation
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// All rights reserved
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// All rights reserved
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//
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//
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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`timescale 1 ns / 10 ps // timescale for following modules
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`timescale 1 ns / 10 ps // timescale for following modules
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module ethmonitor_32 (
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module ethmonitor_32 (
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reset,
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reset,
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tx_clk,
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tx_clk,
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txd,
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txd,
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tx_dv,
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tx_dv,
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tx_er,
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tx_er,
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dst,
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dst,
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src,
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src,
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prmble_len,
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prmble_len,
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pquant,
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pquant,
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vlan_ctl,
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vlan_ctl,
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len,
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len,
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frmtype,
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frmtype,
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payload,
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payload,
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payload_vld,
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payload_vld,
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is_vlan,
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is_vlan,
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is_stack_vlan,
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is_stack_vlan,
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is_pause,
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is_pause,
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crc_err,
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crc_err,
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prmbl_err,
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prmbl_err,
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len_err,
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len_err,
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payload_err,
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payload_err,
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frame_err,
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frame_err,
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pause_op_err,
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pause_op_err,
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pause_dst_err,
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pause_dst_err,
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mac_err,
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mac_err,
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end_err,
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end_err,
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jumbo_en,
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jumbo_en,
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data_only,
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data_only,
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frm_rcvd);
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frm_rcvd);
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parameter ENABLE_SHIFT16 = 1'b 0;
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parameter ENABLE_SHIFT16 = 1'b 0;
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input reset; // active high
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input reset; // active high
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input tx_clk;
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input tx_clk;
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input [7:0] txd;
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input [7:0] txd;
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input tx_dv;
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input tx_dv;
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input tx_er;
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input tx_er;
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output [47:0] dst; // destination address
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output [47:0] dst; // destination address
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output [47:0] src; // source address
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output [47:0] src; // source address
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output [13:0] prmble_len; // length of preamble
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output [13:0] prmble_len; // length of preamble
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output [15:0] pquant; // Pause Quanta value
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output [15:0] pquant; // Pause Quanta value
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output [15:0] vlan_ctl; // VLAN control info
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output [15:0] vlan_ctl; // VLAN control info
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output [15:0] len; // Length of payload
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output [15:0] len; // Length of payload
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output [15:0] frmtype; // if non-null: type field instead length
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output [15:0] frmtype; // if non-null: type field instead length
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output [7:0] payload;
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output [7:0] payload;
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output payload_vld;
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output payload_vld;
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output is_vlan;
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output is_vlan;
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output is_stack_vlan;
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output is_stack_vlan;
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output is_pause;
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output is_pause;
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output crc_err;
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output crc_err;
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output prmbl_err;
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output prmbl_err;
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output len_err;
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output len_err;
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output payload_err;
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output payload_err;
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output frame_err;
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output frame_err;
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output pause_op_err;
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output pause_op_err;
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output pause_dst_err;
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output pause_dst_err;
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output mac_err;
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output mac_err;
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output end_err;
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output end_err;
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input jumbo_en;
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input jumbo_en;
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input data_only;
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input data_only;
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output frm_rcvd;
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output frm_rcvd;
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// GMII transmit interface: To be connected to MAC TX
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// GMII transmit interface: To be connected to MAC TX
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wire [47:0] dst;
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wire [47:0] dst;
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reg [47:0] src;
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reg [47:0] src;
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wire [13:0] prmble_len;
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wire [13:0] prmble_len;
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reg [15:0] pquant;
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reg [15:0] pquant;
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reg [15:0] vlan_ctl;
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reg [15:0] vlan_ctl;
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wire [15:0] len;
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wire [15:0] len;
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wire [15:0] frmtype;
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wire [15:0] frmtype;
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reg [7:0] payload;
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reg [7:0] payload;
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// Indicators
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// Indicators
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reg payload_vld;
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reg payload_vld;
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wire is_vlan;
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wire is_vlan;
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wire is_stack_vlan;
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wire is_stack_vlan;
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wire is_pause;
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wire is_pause;
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reg crc_err;
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reg crc_err;
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reg prmbl_err;
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reg prmbl_err;
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reg len_err;
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reg len_err;
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reg payload_err;
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reg payload_err;
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reg frame_err;
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reg frame_err;
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reg pause_op_err;
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reg pause_op_err;
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reg pause_dst_err;
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reg pause_dst_err;
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reg mac_err;
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reg mac_err;
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// Control
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// Control
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reg end_err;
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reg end_err;
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reg frm_rcvd;
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reg frm_rcvd;
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reg [13:0] iprmble_len; // length of preamble
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reg [13:0] iprmble_len; // length of preamble
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reg [15:0] ifrmtype;
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reg [15:0] ifrmtype;
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reg [15:0] ilen;
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reg [15:0] ilen;
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reg [47:0] idst;
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reg [47:0] idst;
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reg iis_vlan;
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reg iis_vlan;
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reg iis_stack_vlan;
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reg iis_stack_vlan;
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reg iis_pause;
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reg iis_pause;
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// internal
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// internal
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// TYPE state_typ:
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// TYPE state_typ:
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parameter state_typ_s_idle = 0;
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parameter state_typ_s_idle = 0;
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parameter state_typ_s_prmbl = 1;
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parameter state_typ_s_prmbl = 1;
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parameter state_typ_s_dst = 2;
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parameter state_typ_s_dst = 2;
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parameter state_typ_s_src = 3;
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parameter state_typ_s_src = 3;
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parameter state_typ_s_typelen = 4;
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parameter state_typ_s_typelen = 4;
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parameter state_typ_s_pause = 5;
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parameter state_typ_s_pause = 5;
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parameter state_typ_s_tag = 6;
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parameter state_typ_s_tag = 6;
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parameter state_typ_s_len = 7;
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parameter state_typ_s_len = 7;
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parameter state_typ_s_data = 8;
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parameter state_typ_s_data = 8;
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parameter state_typ_s_pad = 9;
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parameter state_typ_s_pad = 9;
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parameter state_typ_s_crc = 10;
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parameter state_typ_s_crc = 10;
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parameter state_typ_s_abort = 11;
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parameter state_typ_s_abort = 11;
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parameter state_typ_s_utype = 12;
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parameter state_typ_s_utype = 12;
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parameter state_typ_s_Dword32Aligned = 13;
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parameter state_typ_s_Dword32Aligned = 13;
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reg [3:0] state;
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reg [3:0] state;
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reg [3:0] last_state;
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reg [3:0] last_state;
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reg last_tx_dv; // follows tx_dv with one cycle delay
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reg last_tx_dv; // follows tx_dv with one cycle delay
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reg [31:0] crc32;
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reg [31:0] crc32;
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reg [31:0] count;
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reg [31:0] count;
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reg [31:0] poscnt; // position in frame starts at first dst byte
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reg [31:0] poscnt; // position in frame starts at first dst byte
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reg [7:0] datacnt; // counter to verify payload
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reg [7:0] datacnt; // counter to verify payload
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reg [7:0] datainc; // counter increment
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reg [7:0] datainc; // counter increment
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wire tx_sof; // start of frame indicator for 1 clk cycle with 1st byte
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wire tx_sof; // start of frame indicator for 1 clk cycle with 1st byte
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reg tx_dst; // start of frame indicator for 1 clk cycle with 1st byte
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reg tx_dst; // start of frame indicator for 1 clk cycle with 1st byte
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// connect permanent port signals
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// connect permanent port signals
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// ------------------------------
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// ------------------------------
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reg [31:0] process_3_crctmp;
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reg [31:0] process_3_crctmp;
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reg [3:0] V2V_process_3_i;
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reg [3:0] V2V_process_3_i;
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integer process_8_ix;
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integer process_8_ix;
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integer process_9_ix;
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integer process_9_ix;
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reg process_9_ln;
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reg process_9_ln;
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integer process_12_ix;
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integer process_12_ix;
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integer process_10_ix;
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integer process_10_ix;
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integer process_11_hi;
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integer process_11_hi;
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integer process_11_lo;
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integer process_11_lo;
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reg [31:0] process_11_cnttmp;
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reg [31:0] process_11_cnttmp;
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integer process_11_i;
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integer process_11_i;
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integer process_11_flen;
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integer process_11_flen;
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assign prmble_len = iprmble_len;
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assign prmble_len = iprmble_len;
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assign frmtype = ifrmtype;
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assign frmtype = ifrmtype;
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assign len = ilen;
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assign len = ilen;
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assign dst = idst;
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assign dst = idst;
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assign is_vlan = iis_vlan;
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assign is_vlan = iis_vlan;
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assign is_stack_vlan = iis_stack_vlan;
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assign is_stack_vlan = iis_stack_vlan;
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assign is_pause = iis_pause;
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assign is_pause = iis_pause;
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// generate tx start pulse
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// generate tx start pulse
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// ----------------------
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// ----------------------
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assign tx_sof = ~last_tx_dv & tx_dv; // pulse with first byte 0 to 1 change
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assign tx_sof = ~last_tx_dv & tx_dv; // pulse with first byte 0 to 1 change
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// generate pulse start of destination address
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// generate pulse start of destination address
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// --------------------
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// --------------------
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always @(last_state or state)
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always @(last_state or state)
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begin : process_1
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begin : process_1
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if (last_state != state_typ_s_dst & state == state_typ_s_dst)
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if (last_state != state_typ_s_dst & state == state_typ_s_dst)
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begin
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begin
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tx_dst <= 1'b 1;
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tx_dst <= 1'b 1;
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end
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end
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else
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else
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begin
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begin
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tx_dst <= 1'b 0;
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tx_dst <= 1'b 0;
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end
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end
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end
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end
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// ------------------------------------------
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// ------------------------------------------
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// capture tx_er indicator
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// capture tx_er indicator
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// ------------------------------------------
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// ------------------------------------------
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always @(posedge tx_clk or posedge reset)
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always @(posedge tx_clk or posedge reset)
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begin : process_2
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begin : process_2
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if (reset == 1'b 1)
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if (reset == 1'b 1)
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begin
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begin
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mac_err <= 1'b 0;
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mac_err <= 1'b 0;
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last_tx_dv <= 1'b 0;
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last_tx_dv <= 1'b 0;
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end
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end
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else
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else
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begin
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begin
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if (tx_sof == 1'b 1)
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if (tx_sof == 1'b 1)
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begin
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begin
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mac_err <= 1'b 0; // reset indicator at start of new receive
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mac_err <= 1'b 0; // reset indicator at start of new receive
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end
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end
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else if (tx_er == 1'b 1 )
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else if (tx_er == 1'b 1 )
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begin
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begin
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mac_err <= 1'b 1; // capture one or many
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mac_err <= 1'b 1; // capture one or many
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end
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end
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last_tx_dv <= tx_dv;
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last_tx_dv <= tx_dv;
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end
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end
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end
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end
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// ----------------------------------------------
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// ----------------------------------------------
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// CRC calculation over all bytes except preamble
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// CRC calculation over all bytes except preamble
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// ----------------------------------------------
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// ----------------------------------------------
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always @(posedge tx_clk or posedge reset)
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always @(posedge tx_clk or posedge reset)
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begin : process_3
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begin : process_3
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if (reset == 1'b 1)
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if (reset == 1'b 1)
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begin
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begin
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crc32 <= {32{1'b 1}};
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crc32 <= {32{1'b 1}};
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crc_err <= 1'b 0;
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crc_err <= 1'b 0;
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end
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end
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else
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else
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begin
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begin
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// need it ahead
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// need it ahead
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if (tx_dst == 1'b 1 | state != state_typ_s_idle &
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if (tx_dst == 1'b 1 | state != state_typ_s_idle &
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state != state_typ_s_prmbl & state != state_typ_s_utype |
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state != state_typ_s_prmbl & state != state_typ_s_utype |
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state == state_typ_s_utype & tx_dv == 1'b 1)
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state == state_typ_s_utype & tx_dv == 1'b 1)
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begin
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begin
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// push all inclusive CRC bytes
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// push all inclusive CRC bytes
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// preset CRC or load current value
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// preset CRC or load current value
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if (tx_dst == 1'b 1)
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if (tx_dst == 1'b 1)
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begin
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begin
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// first data, preset CRC
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// first data, preset CRC
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process_3_crctmp = {32{1'b 1}};
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process_3_crctmp = {32{1'b 1}};
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end
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end
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else
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else
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begin
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begin
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process_3_crctmp = crc32;
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process_3_crctmp = crc32;
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end
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end
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// calculate next step
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// calculate next step
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for (V2V_process_3_i = 0; V2V_process_3_i <= 7; V2V_process_3_i = V2V_process_3_i + 1)
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for (V2V_process_3_i = 0; V2V_process_3_i <= 7; V2V_process_3_i = V2V_process_3_i + 1)
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begin
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begin
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if ((txd[V2V_process_3_i] ^ process_3_crctmp[31]) == 1'b 1)
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if ((txd[V2V_process_3_i] ^ process_3_crctmp[31]) == 1'b 1)
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begin
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begin
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process_3_crctmp = (process_3_crctmp << 1); // shift in a 0, will be xor'ed to 1 by the polynom
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process_3_crctmp = (process_3_crctmp << 1); // shift in a 0, will be xor'ed to 1 by the polynom
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process_3_crctmp = process_3_crctmp ^ 32'h 04C11DB7;
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process_3_crctmp = process_3_crctmp ^ 32'h 04C11DB7;
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end
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end
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else
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else
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begin
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begin
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process_3_crctmp = (process_3_crctmp << 1); // shift in a 0
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process_3_crctmp = (process_3_crctmp << 1); // shift in a 0
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end
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end
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end
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end
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// process all bits we have here
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// process all bits we have here
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crc32 <= process_3_crctmp; // remember current value
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crc32 <= process_3_crctmp; // remember current value
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// check if CRC is valid
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// check if CRC is valid
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if (process_3_crctmp == 32'h C704DD7B)
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if (process_3_crctmp == 32'h C704DD7B)
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begin
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begin
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crc_err <= 1'b 0;
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crc_err <= 1'b 0;
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end
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end
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else
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else
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begin
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begin
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crc_err <= 1'b 1;
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crc_err <= 1'b 1;
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end
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end
|
end
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end
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end
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end
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end
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end
|
// ----------------------------------------------
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// ----------------------------------------------
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// Extract RX Payload on payload bus and check payload errors:
|
// Extract RX Payload on payload bus and check payload errors:
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// * first byte is counter initialization
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// * first byte is counter initialization
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// * second byte is counter increment
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// * second byte is counter increment
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// * data begins from 3rd byte on
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// * data begins from 3rd byte on
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// ----------------------------------------------
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// ----------------------------------------------
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always @(posedge tx_clk or posedge reset)
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always @(posedge tx_clk or posedge reset)
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begin : process_4
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begin : process_4
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if (reset == 1'b 1)
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if (reset == 1'b 1)
|
begin
|
begin
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payload <= {8{1'b 0}};
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payload <= {8{1'b 0}};
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payload_vld <= 1'b 0;
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payload_vld <= 1'b 0;
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payload_err <= 1'b 0;
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payload_err <= 1'b 0;
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datacnt <= 0;
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datacnt <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (state == state_typ_s_typelen)
|
if (state == state_typ_s_typelen)
|
begin
|
begin
|
payload_err <= 1'b 0; // reset as a frame of length 0 will not get into S_DATA.
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payload_err <= 1'b 0; // reset as a frame of length 0 will not get into S_DATA.
|
end
|
end
|
if (state == state_typ_s_data)
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if (state == state_typ_s_data)
|
begin
|
begin
|
payload <= txd;
|
payload <= txd;
|
payload_vld <= 1'b 1;
|
payload_vld <= 1'b 1;
|
if (count == 0)
|
if (count == 0)
|
begin
|
begin
|
datacnt <= ({1'b 0, txd}); // load counter
|
datacnt <= ({1'b 0, txd}); // load counter
|
payload_err <= 1'b 0;
|
payload_err <= 1'b 0;
|
end
|
end
|
else if (count == 1 )
|
else if (count == 1 )
|
begin
|
begin
|
datainc <= ({1'b 0, txd}); // load increment
|
datainc <= ({1'b 0, txd}); // load increment
|
// verify payload contents
|
// verify payload contents
|
end
|
end
|
else
|
else
|
begin
|
begin
|
datacnt <= (datacnt + datainc) % 256;
|
datacnt <= (datacnt + datainc) % 256;
|
if (datacnt != ({1'b 0, txd}))
|
if (datacnt != ({1'b 0, txd}))
|
begin
|
begin
|
payload_err <= 1'b 1;
|
payload_err <= 1'b 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
payload <= {8{1'b 0}};
|
payload <= {8{1'b 0}};
|
payload_vld <= 1'b 0;
|
payload_vld <= 1'b 0;
|
end
|
end
|
end
|
end
|
end
|
end
|
// ----------------------------------------------
|
// ----------------------------------------------
|
// Position Counter: Starts with first octet of destination address
|
// Position Counter: Starts with first octet of destination address
|
// ----------------------------------------------
|
// ----------------------------------------------
|
always @(posedge tx_clk or posedge reset)
|
always @(posedge tx_clk or posedge reset)
|
begin : process_5
|
begin : process_5
|
if (reset == 1'b 1)
|
if (reset == 1'b 1)
|
begin
|
begin
|
poscnt <= 0;
|
poscnt <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (tx_dst == 1'b 1)
|
if (tx_dst == 1'b 1)
|
begin
|
begin
|
// reset at start of DST
|
// reset at start of DST
|
poscnt <= 1;
|
poscnt <= 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (poscnt < 65535)
|
if (poscnt < 65535)
|
begin
|
begin
|
poscnt <= poscnt + 1'b 1;
|
poscnt <= poscnt + 1'b 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
// ----------------------------------------------
|
// ----------------------------------------------
|
// End of Frame:
|
// End of Frame:
|
// change from non-idle to idle indicates something was received
|
// change from non-idle to idle indicates something was received
|
// if dv is still asserted this is an end error
|
// if dv is still asserted this is an end error
|
// ----------------------------------------------
|
// ----------------------------------------------
|
always @(posedge tx_clk or posedge reset)
|
always @(posedge tx_clk or posedge reset)
|
begin : process_6
|
begin : process_6
|
if (reset == 1'b 1)
|
if (reset == 1'b 1)
|
begin
|
begin
|
frm_rcvd <= 1'b 0;
|
frm_rcvd <= 1'b 0;
|
end_err <= 1'b 0;
|
end_err <= 1'b 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (last_state != state_typ_s_idle & state == state_typ_s_idle)
|
if (last_state != state_typ_s_idle & state == state_typ_s_idle)
|
begin
|
begin
|
frm_rcvd <= 1'b 1;
|
frm_rcvd <= 1'b 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
frm_rcvd <= 1'b 0;
|
frm_rcvd <= 1'b 0;
|
end
|
end
|
if (tx_sof == 1'b 1)
|
if (tx_sof == 1'b 1)
|
begin
|
begin
|
end_err <= 1'b 0;
|
end_err <= 1'b 0;
|
end
|
end
|
else if (last_state != state_typ_s_idle & state == state_typ_s_idle &
|
else if (last_state != state_typ_s_idle & state == state_typ_s_idle &
|
tx_dv == 1'b 1 )
|
tx_dv == 1'b 1 )
|
begin
|
begin
|
end_err <= 1'b 1; // dv still asserted even after nothing more expected
|
end_err <= 1'b 1; // dv still asserted even after nothing more expected
|
end
|
end
|
end
|
end
|
end
|
end
|
// ----------------------------------------------
|
// ----------------------------------------------
|
// Preamble check
|
// Preamble check
|
// ----------------------------------------------
|
// ----------------------------------------------
|
always @(posedge tx_clk or posedge reset)
|
always @(posedge tx_clk or posedge reset)
|
begin : process_7
|
begin : process_7
|
if (reset == 1'b 1)
|
if (reset == 1'b 1)
|
begin
|
begin
|
prmbl_err <= 1'b 0;
|
prmbl_err <= 1'b 0;
|
iprmble_len <= 0;
|
iprmble_len <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (tx_sof == 1'b 1)
|
if (tx_sof == 1'b 1)
|
begin
|
begin
|
if (txd != 8'h 55)
|
if (txd != 8'h 55)
|
begin
|
begin
|
prmbl_err <= 1'b 1;
|
prmbl_err <= 1'b 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
prmbl_err <= 1'b 0; // reset usually
|
prmbl_err <= 1'b 0; // reset usually
|
end
|
end
|
if (data_only == 1'b 1)
|
if (data_only == 1'b 1)
|
begin
|
begin
|
iprmble_len <= 0;
|
iprmble_len <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
iprmble_len <= 1;
|
iprmble_len <= 1;
|
end
|
end
|
end
|
end
|
else if (state == state_typ_s_prmbl )
|
else if (state == state_typ_s_prmbl )
|
begin
|
begin
|
if (txd != 8'h 55 & txd != 8'h D5)
|
if (txd != 8'h 55 & txd != 8'h D5)
|
begin
|
begin
|
prmbl_err <= 1'b 1;
|
prmbl_err <= 1'b 1;
|
end
|
end
|
iprmble_len <= iprmble_len + 1'b 1;
|
iprmble_len <= iprmble_len + 1'b 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
// ----------------------------------------------
|
// ----------------------------------------------
|
// Extract Source and Destination addresses
|
// Extract Source and Destination addresses
|
// ----------------------------------------------
|
// ----------------------------------------------
|
always @(posedge tx_clk or posedge reset)
|
always @(posedge tx_clk or posedge reset)
|
begin : process_8
|
begin : process_8
|
if (reset == 1'b 1)
|
if (reset == 1'b 1)
|
begin
|
begin
|
idst <= {48{1'b 0}};
|
idst <= {48{1'b 0}};
|
src <= {48{1'b 0}};
|
src <= {48{1'b 0}};
|
end
|
end
|
else
|
else
|
begin
|
begin
|
process_8_ix = count * 8;
|
process_8_ix = count * 8;
|
|
|
if (tx_sof == 1'b 1 & data_only == 1'b 1 & state == state_typ_s_Dword32Aligned & ENABLE_SHIFT16 == 1'b1)
|
if (tx_sof == 1'b 1 & data_only == 1'b 1 & state == state_typ_s_Dword32Aligned & ENABLE_SHIFT16 == 1'b1)
|
begin
|
begin
|
case (count)
|
case (count)
|
1'b 0 : ;
|
1'b 0 : ;
|
1'b 1 : ;
|
1'b 1 : ;
|
default:;
|
default:;
|
endcase
|
endcase
|
end
|
end
|
if (tx_sof == 1'b 0 & data_only == 1'b 1 & ENABLE_SHIFT16 == 1'b1 & state == state_typ_s_dst)
|
if (tx_sof == 1'b 0 & data_only == 1'b 1 & ENABLE_SHIFT16 == 1'b1 & state == state_typ_s_dst)
|
begin
|
begin
|
case (count)
|
case (count)
|
1'b 0:
|
1'b 0:
|
begin
|
begin
|
idst[7:0] <= txd[7:0];
|
idst[7:0] <= txd[7:0];
|
end
|
end
|
1'b 1:
|
1'b 1:
|
begin
|
begin
|
idst[15:8] <= txd[7:0];
|
idst[15:8] <= txd[7:0];
|
end
|
end
|
2'b 10:
|
2'b 10:
|
begin
|
begin
|
idst[23:16] <= txd[7:0];
|
idst[23:16] <= txd[7:0];
|
end
|
end
|
2'b 11:
|
2'b 11:
|
begin
|
begin
|
idst[31:24] <= txd[7:0];
|
idst[31:24] <= txd[7:0];
|
end
|
end
|
3'b 100:
|
3'b 100:
|
begin
|
begin
|
idst[39:32] <= txd[7:0];
|
idst[39:32] <= txd[7:0];
|
end
|
end
|
3'b 101:
|
3'b 101:
|
begin
|
begin
|
idst[47:40] <= txd[7:0];
|
idst[47:40] <= txd[7:0];
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase end
|
endcase end
|
|
|
|
|
if (tx_sof == 1'b 1 & data_only == 1'b 1 & ENABLE_SHIFT16 == 1'b0 | state == state_typ_s_dst)
|
if (tx_sof == 1'b 1 & data_only == 1'b 1 & ENABLE_SHIFT16 == 1'b0 | state == state_typ_s_dst)
|
begin
|
begin
|
case (count)
|
case (count)
|
1'b 0:
|
1'b 0:
|
begin
|
begin
|
idst[7:0] <= txd[7:0];
|
idst[7:0] <= txd[7:0];
|
end
|
end
|
1'b 1:
|
1'b 1:
|
begin
|
begin
|
idst[15:8] <= txd[7:0];
|
idst[15:8] <= txd[7:0];
|
end
|
end
|
2'b 10:
|
2'b 10:
|
begin
|
begin
|
idst[23:16] <= txd[7:0];
|
idst[23:16] <= txd[7:0];
|
end
|
end
|
2'b 11:
|
2'b 11:
|
begin
|
begin
|
idst[31:24] <= txd[7:0];
|
idst[31:24] <= txd[7:0];
|
end
|
end
|
3'b 100:
|
3'b 100:
|
begin
|
begin
|
idst[39:32] <= txd[7:0];
|
idst[39:32] <= txd[7:0];
|
end
|
end
|
3'b 101:
|
3'b 101:
|
begin
|
begin
|
idst[47:40] <= txd[7:0];
|
idst[47:40] <= txd[7:0];
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase end
|
endcase end
|
if (state == state_typ_s_src)
|
if (state == state_typ_s_src)
|
begin
|
begin
|
case (count)
|
case (count)
|
1'b 0:
|
1'b 0:
|
begin
|
begin
|
src[7:0] <= txd[7:0];
|
src[7:0] <= txd[7:0];
|
end
|
end
|
1'b 1:
|
1'b 1:
|
begin
|
begin
|
src[15:8] <= txd[7:0];
|
src[15:8] <= txd[7:0];
|
end
|
end
|
2'b 10:
|
2'b 10:
|
begin
|
begin
|
src[23:16] <= txd[7:0];
|
src[23:16] <= txd[7:0];
|
end
|
end
|
2'b 11:
|
2'b 11:
|
begin
|
begin
|
src[31:24] <= txd[7:0];
|
src[31:24] <= txd[7:0];
|
end
|
end
|
3'b 100:
|
3'b 100:
|
begin
|
begin
|
src[39:32] <= txd[7:0];
|
src[39:32] <= txd[7:0];
|
end
|
end
|
3'b 101:
|
3'b 101:
|
begin
|
begin
|
src[47:40] <= txd[7:0];
|
src[47:40] <= txd[7:0];
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
// ----------------------------------------------
|
// ----------------------------------------------
|
// Extract Length/Type field and VLAN Tag identifier
|
// Extract Length/Type field and VLAN Tag identifier
|
// ----------------------------------------------
|
// ----------------------------------------------
|
|
|
always @(posedge tx_clk or posedge reset)
|
always @(posedge tx_clk or posedge reset)
|
begin : process_12
|
begin : process_12
|
if (reset == 1'b 1)
|
if (reset == 1'b 1)
|
begin
|
begin
|
ilen <= {16{1'b 0}};
|
ilen <= {16{1'b 0}};
|
ifrmtype <= {16{1'b 0}};
|
ifrmtype <= {16{1'b 0}};
|
vlan_ctl <= {16{1'b 0}};
|
vlan_ctl <= {16{1'b 0}};
|
iis_vlan <= 1'b 0;
|
iis_vlan <= 1'b 0;
|
len_err <= 1'b 0;
|
len_err <= 1'b 0;
|
iis_stack_vlan <= 1'b0;
|
iis_stack_vlan <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
process_12_ix = 4'b 1000 - count * 8;
|
process_12_ix = 4'b 1000 - count * 8;
|
// if( tx_sof_d = '1' ) then -- clear all on start of every frame
|
// if( tx_sof_d = '1' ) then -- clear all on start of every frame
|
//
|
//
|
// ilen <= (others => '0');
|
// ilen <= (others => '0');
|
// ifrmtype <= (others => '0');
|
// ifrmtype <= (others => '0');
|
// vlan_ctl <= (others => '0');
|
// vlan_ctl <= (others => '0');
|
// iis_vlan <= '0';
|
// iis_vlan <= '0';
|
//
|
//
|
// end if;
|
// end if;
|
if (state == state_typ_s_typelen)
|
if (state == state_typ_s_typelen)
|
begin
|
begin
|
// if in type/len set both
|
// if in type/len set both
|
case (count)
|
case (count)
|
1'b 0:
|
1'b 0:
|
begin
|
begin
|
ifrmtype[15:8] <= txd;
|
ifrmtype[15:8] <= txd;
|
ilen[15:8] <= txd;
|
ilen[15:8] <= txd;
|
end
|
end
|
1'b 1:
|
1'b 1:
|
begin
|
begin
|
ifrmtype[7:0] <= txd;
|
ifrmtype[7:0] <= txd;
|
ilen[7:0] <= txd;
|
ilen[7:0] <= txd;
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
vlan_ctl <= {16{1'b 0}}; // clear at start of new frame (at SOF it is too early)
|
vlan_ctl <= {16{1'b 0}}; // clear at start of new frame (at SOF it is too early)
|
iis_vlan <= 1'b 0;
|
iis_vlan <= 1'b 0;
|
len_err <= 1'b 0;
|
len_err <= 1'b 0;
|
end
|
end
|
|
|
if(state==state_typ_s_typelen)
|
if(state==state_typ_s_typelen)
|
begin
|
begin
|
|
|
iis_stack_vlan <= 1'b0 ;
|
iis_stack_vlan <= 1'b0 ;
|
|
|
end
|
end
|
else if (last_state == state_typ_s_len & state == state_typ_s_tag)
|
else if (last_state == state_typ_s_len & state == state_typ_s_tag)
|
begin
|
begin
|
|
|
iis_stack_vlan <= 1'b1 ;
|
iis_stack_vlan <= 1'b1 ;
|
|
|
end
|
end
|
|
|
else if (state == state_typ_s_len )
|
else if (state == state_typ_s_len )
|
begin
|
begin
|
// in len again, set len independently
|
// in len again, set len independently
|
case (count)
|
case (count)
|
1'b 0:
|
1'b 0:
|
begin
|
begin
|
ifrmtype[15:8] <= txd;
|
ifrmtype[15:8] <= txd;
|
ilen[15:8] <= txd;
|
ilen[15:8] <= txd;
|
end
|
end
|
1'b 1:
|
1'b 1:
|
begin
|
begin
|
ifrmtype[7:0] <= txd;
|
ifrmtype[7:0] <= txd;
|
ilen[7:0] <= txd;
|
ilen[7:0] <= txd;
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
else if (state == state_typ_s_tag )
|
else if (state == state_typ_s_tag )
|
begin
|
begin
|
iis_vlan <= 1'b 1;
|
iis_vlan <= 1'b 1;
|
case (count)
|
case (count)
|
1'b 0:
|
1'b 0:
|
begin
|
begin
|
vlan_ctl[15:8] <= txd; // ilen(ix+7 downto ix) <= txd;
|
vlan_ctl[15:8] <= txd; // ilen(ix+7 downto ix) <= txd;
|
end
|
end
|
1'b 1:
|
1'b 1:
|
begin
|
begin
|
vlan_ctl[7:0] <= txd;
|
vlan_ctl[7:0] <= txd;
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase end
|
endcase end
|
// verify length at end of frame for normal frames (length 46... max and not a type)
|
// verify length at end of frame for normal frames (length 46... max and not a type)
|
if (last_state == state_typ_s_crc & state == state_typ_s_idle &
|
if (last_state == state_typ_s_crc & state == state_typ_s_idle &
|
iis_pause == 1'b 0 & (iis_vlan == 1'b 0 &
|
iis_pause == 1'b 0 & (iis_vlan == 1'b 0 &
|
ilen > 45 | iis_vlan == 1'b 1 &
|
ilen > 45 | iis_vlan == 1'b 1 &
|
ilen > 41))
|
ilen > 41))
|
begin
|
begin
|
// verify integrity of length field
|
// verify integrity of length field
|
if (tx_dv == 1'b 1 |
|
if (tx_dv == 1'b 1 |
|
iis_stack_vlan == 1'b 1 & ilen != poscnt - 5'b 11010 |
|
iis_stack_vlan == 1'b 1 & ilen != poscnt - 5'b 11010 |
|
(iis_vlan == 1'b 1 & iis_stack_vlan == 1'b 0) & ilen != poscnt - 5'b 10110 |
|
(iis_vlan == 1'b 1 & iis_stack_vlan == 1'b 0) & ilen != poscnt - 5'b 10110 |
|
iis_vlan == 1'b 0 & ilen != poscnt - 5'b 10010)
|
iis_vlan == 1'b 0 & ilen != poscnt - 5'b 10010)
|
begin
|
begin
|
len_err <= 1'b 1;
|
len_err <= 1'b 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
len_err <= 1'b 0;
|
len_err <= 1'b 0;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
// ----------------------------------------------
|
// ----------------------------------------------
|
// Extract Pause frame indication,
|
// Extract Pause frame indication,
|
// opcode error,
|
// opcode error,
|
// destination address error,
|
// destination address error,
|
// and Pause Quanta
|
// and Pause Quanta
|
// ----------------------------------------------
|
// ----------------------------------------------
|
always @(posedge tx_clk or posedge reset)
|
always @(posedge tx_clk or posedge reset)
|
begin : process_13
|
begin : process_13
|
if (reset == 1'b 1)
|
if (reset == 1'b 1)
|
begin
|
begin
|
pquant <= {16{1'b 0}};
|
pquant <= {16{1'b 0}};
|
iis_pause <= 1'b 0;
|
iis_pause <= 1'b 0;
|
pause_op_err <= 1'b 0;
|
pause_op_err <= 1'b 0;
|
pause_dst_err <= 1'b 0;
|
pause_dst_err <= 1'b 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (tx_sof == 1'b 1)
|
if (tx_sof == 1'b 1)
|
begin
|
begin
|
iis_pause <= 1'b 0; // clear at start of frame
|
iis_pause <= 1'b 0; // clear at start of frame
|
pause_op_err <= 1'b 0;
|
pause_op_err <= 1'b 0;
|
pause_dst_err <= 1'b 0;
|
pause_dst_err <= 1'b 0;
|
end
|
end
|
if (state == state_typ_s_pause)
|
if (state == state_typ_s_pause)
|
begin
|
begin
|
iis_pause <= 1'b 1;
|
iis_pause <= 1'b 1;
|
//if (count >= 2)
|
//if (count >= 2)
|
//begin
|
//begin
|
// pick octets after opcode
|
// pick octets after opcode
|
case (count)
|
case (count)
|
2'b 11:
|
2'b 11:
|
begin
|
begin
|
pquant[15:8] <= txd;
|
pquant[15:8] <= txd;
|
end
|
end
|
1'b 0:
|
1'b 0:
|
begin
|
begin
|
pquant[7:0] <= txd;
|
pquant[7:0] <= txd;
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
//end
|
//end
|
if (count == 0 & txd != 8'h 00 |
|
if (count == 0 & txd != 8'h 00 |
|
count == 1 & txd != 8'h 01 )
|
count == 1 & txd != 8'h 01 )
|
begin
|
begin
|
pause_op_err <= 1'b 1;
|
pause_op_err <= 1'b 1;
|
end
|
end
|
if (idst != 48'h 010000c28001)
|
if (idst != 48'h 010000c28001)
|
begin
|
begin
|
// 01-80-c2-00-00-01 is standard !
|
// 01-80-c2-00-00-01 is standard !
|
pause_dst_err <= 1'b 1;
|
pause_dst_err <= 1'b 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
// ----------------------------------------------
|
// ----------------------------------------------
|
// Monitor State Machine
|
// Monitor State Machine
|
// ----------------------------------------------
|
// ----------------------------------------------
|
always @(posedge tx_clk or posedge reset)
|
always @(posedge tx_clk or posedge reset)
|
begin : process_11
|
begin : process_11
|
if (reset == 1'b 1)
|
if (reset == 1'b 1)
|
begin
|
begin
|
state <= state_typ_s_idle;
|
state <= state_typ_s_idle;
|
last_state <= state_typ_s_idle;
|
last_state <= state_typ_s_idle;
|
count <= 0;
|
count <= 0;
|
frame_err <= 1'b 0; // state machine abort indicator
|
frame_err <= 1'b 0; // state machine abort indicator
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// remember last state and increment internal counter
|
// remember last state and increment internal counter
|
last_state <= state;
|
last_state <= state;
|
if (count < 65535)
|
if (count < 65535)
|
begin
|
begin
|
process_11_cnttmp = count + 1'b 1;
|
process_11_cnttmp = count + 1'b 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
process_11_cnttmp = count;
|
process_11_cnttmp = count;
|
end
|
end
|
// Abort detection: If enable goes low in middle of frame
|
// Abort detection: If enable goes low in middle of frame
|
if (state != state_typ_s_idle & state != state_typ_s_abort &
|
if (state != state_typ_s_idle & state != state_typ_s_abort &
|
state != state_typ_s_utype & tx_dv == 1'b 0)
|
state != state_typ_s_utype & tx_dv == 1'b 0)
|
begin
|
begin
|
state <= state_typ_s_abort;
|
state <= state_typ_s_abort;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
case (state)
|
case (state)
|
state_typ_s_abort:
|
state_typ_s_abort:
|
begin
|
begin
|
if (tx_dv == 1'b 1)
|
if (tx_dv == 1'b 1)
|
begin
|
begin
|
if (last_tx_dv == 1'b 0 & data_only == 1'b 1)
|
if (last_tx_dv == 1'b 0 & data_only == 1'b 1)
|
begin
|
begin
|
// only 1 clock cycle inbetween
|
// only 1 clock cycle inbetween
|
if (ENABLE_SHIFT16 == 1'b0)
|
if (ENABLE_SHIFT16 == 1'b0)
|
state <= state_typ_s_dst;
|
state <= state_typ_s_dst;
|
else
|
else
|
state <= state_typ_s_Dword32Aligned;
|
state <= state_typ_s_Dword32Aligned;
|
|
|
process_11_cnttmp = 1'b 1;
|
process_11_cnttmp = 1'b 1;
|
frame_err <= 1'b 0;
|
frame_err <= 1'b 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
state <= state_typ_s_abort; // wait til tx stops transmission
|
state <= state_typ_s_abort; // wait til tx stops transmission
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
state <= state_typ_s_idle;
|
state <= state_typ_s_idle;
|
end
|
end
|
frame_err <= 1'b 1;
|
frame_err <= 1'b 1;
|
end
|
end
|
state_typ_s_idle:
|
state_typ_s_idle:
|
begin
|
begin
|
if (tx_sof == 1'b 1)
|
if (tx_sof == 1'b 1)
|
begin
|
begin
|
// we miss the very first !
|
// we miss the very first !
|
process_11_cnttmp = 1'b 1; // therefore need to count to 1 immediately
|
process_11_cnttmp = 1'b 1; // therefore need to count to 1 immediately
|
frame_err <= 1'b 0;
|
frame_err <= 1'b 0;
|
if (data_only == 1'b 1)
|
if (data_only == 1'b 1)
|
begin
|
begin
|
// no preamble checking ?
|
// no preamble checking ?
|
if (ENABLE_SHIFT16 == 1'b0)
|
if (ENABLE_SHIFT16 == 1'b0)
|
state <= state_typ_s_dst;
|
state <= state_typ_s_dst;
|
else
|
else
|
state <= state_typ_s_Dword32Aligned;
|
state <= state_typ_s_Dword32Aligned;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
state <= state_typ_s_prmbl;
|
state <= state_typ_s_prmbl;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
process_11_cnttmp = 1'b 0; // keep it to zero always
|
process_11_cnttmp = 1'b 0; // keep it to zero always
|
end
|
end
|
end
|
end
|
state_typ_s_prmbl:
|
state_typ_s_prmbl:
|
begin
|
begin
|
if (txd == 8'h D5)
|
if (txd == 8'h D5)
|
begin
|
begin
|
state <= state_typ_s_dst;
|
state <= state_typ_s_dst;
|
process_11_cnttmp = 1'b 0;
|
process_11_cnttmp = 1'b 0;
|
end
|
end
|
end
|
end
|
|
|
state_typ_s_Dword32Aligned:
|
state_typ_s_Dword32Aligned:
|
begin
|
begin
|
if (count == 1)
|
if (count == 1)
|
begin
|
begin
|
state <= state_typ_s_dst;
|
state <= state_typ_s_dst;
|
process_11_cnttmp = 1'b 0;
|
process_11_cnttmp = 1'b 0;
|
end
|
end
|
end
|
end
|
|
|
state_typ_s_dst:
|
state_typ_s_dst:
|
begin
|
begin
|
if (count == 5)
|
if (count == 5)
|
begin
|
begin
|
state <= state_typ_s_src;
|
state <= state_typ_s_src;
|
process_11_cnttmp = 1'b 0;
|
process_11_cnttmp = 1'b 0;
|
end
|
end
|
end
|
end
|
state_typ_s_src:
|
state_typ_s_src:
|
begin
|
begin
|
if (count == 5)
|
if (count == 5)
|
begin
|
begin
|
state <= state_typ_s_typelen;
|
state <= state_typ_s_typelen;
|
process_11_cnttmp = 1'b 0;
|
process_11_cnttmp = 1'b 0;
|
end
|
end
|
end
|
end
|
state_typ_s_typelen:
|
state_typ_s_typelen:
|
begin
|
begin
|
if (count != 0)
|
if (count != 0)
|
begin
|
begin
|
// second half of 2-octet field
|
// second half of 2-octet field
|
process_11_cnttmp = 1'b 0;
|
process_11_cnttmp = 1'b 0;
|
process_11_flen = ({1'b 0, ilen[15:8], txd}); // need it NOW
|
process_11_flen = ({1'b 0, ilen[15:8], txd}); // need it NOW
|
if (jumbo_en == 1'b 1 & process_11_flen <= 9000 |
|
if (jumbo_en == 1'b 1 & process_11_flen <= 9000 |
|
process_11_flen <= 1500)
|
process_11_flen <= 1500)
|
begin
|
begin
|
// ok normal user frame. check if data or 0 length
|
// ok normal user frame. check if data or 0 length
|
if (process_11_flen != 0)
|
if (process_11_flen != 0)
|
begin
|
begin
|
state <= state_typ_s_data;
|
state <= state_typ_s_data;
|
// no data, PAD or finished
|
// no data, PAD or finished
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (data_only == 1'b 1)
|
if (data_only == 1'b 1)
|
begin
|
begin
|
state <= state_typ_s_idle; // Ok, we are done dont expect anything more
|
state <= state_typ_s_idle; // Ok, we are done dont expect anything more
|
end
|
end
|
else
|
else
|
begin
|
begin
|
state <= state_typ_s_pad; // zero-length frame needs padding
|
state <= state_typ_s_pad; // zero-length frame needs padding
|
end
|
end
|
end
|
end
|
// not normal frame
|
// not normal frame
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (process_11_flen == 16'h 8808)
|
if (process_11_flen == 16'h 8808)
|
begin
|
begin
|
state <= state_typ_s_pause;
|
state <= state_typ_s_pause;
|
end
|
end
|
else if (process_11_flen == 16'h 8100 )
|
else if (process_11_flen == 16'h 8100 )
|
begin
|
begin
|
state <= state_typ_s_tag;
|
state <= state_typ_s_tag;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
state <= state_typ_s_utype; // S_ABORT; -- unknown type
|
state <= state_typ_s_utype; // S_ABORT; -- unknown type
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
state_typ_s_pause:
|
state_typ_s_pause:
|
begin
|
begin
|
if (count >= 3)
|
if (count >= 3)
|
begin
|
begin
|
// need to overread opcode
|
// need to overread opcode
|
state <= state_typ_s_pad;
|
state <= state_typ_s_pad;
|
process_11_cnttmp = 1'b 0;
|
process_11_cnttmp = 1'b 0;
|
end
|
end
|
end
|
end
|
state_typ_s_tag:
|
state_typ_s_tag:
|
begin
|
begin
|
if (count >= 1)
|
if (count >= 1)
|
begin
|
begin
|
state <= state_typ_s_len;
|
state <= state_typ_s_len;
|
process_11_cnttmp = 1'b 0;
|
process_11_cnttmp = 1'b 0;
|
end
|
end
|
end
|
end
|
state_typ_s_len:
|
state_typ_s_len:
|
begin
|
begin
|
if (count >= 1)
|
if (count >= 1)
|
begin
|
begin
|
// Length after VLAN TAG
|
// Length after VLAN TAG
|
process_11_cnttmp = 1'b 0;
|
process_11_cnttmp = 1'b 0;
|
process_11_flen = ({1'b 0, ilen[15:8], txd}); // need it NOW
|
process_11_flen = ({1'b 0, ilen[15:8], txd}); // need it NOW
|
|
|
if ( process_11_flen == 16'h8100)
|
if ( process_11_flen == 16'h8100)
|
begin
|
begin
|
|
|
state <= state_typ_s_tag;
|
state <= state_typ_s_tag;
|
|
|
end
|
end
|
else if (process_11_flen != 0 & (jumbo_en == 1'b 1 &
|
else if (process_11_flen != 0 & (jumbo_en == 1'b 1 &
|
process_11_flen > 9000 | jumbo_en == 1'b 0 &
|
process_11_flen > 9000 | jumbo_en == 1'b 0 &
|
process_11_flen > 1500))
|
process_11_flen > 1500))
|
begin
|
begin
|
state <= state_typ_s_utype;
|
state <= state_typ_s_utype;
|
end
|
end
|
else if (process_11_flen != 0 )
|
else if (process_11_flen != 0 )
|
begin
|
begin
|
state <= state_typ_s_data;
|
state <= state_typ_s_data;
|
// no data, PAD or finished
|
// no data, PAD or finished
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (data_only == 1'b 1)
|
if (data_only == 1'b 1)
|
begin
|
begin
|
state <= state_typ_s_idle; // Ok, we are done dont expect CRC
|
state <= state_typ_s_idle; // Ok, we are done dont expect CRC
|
end
|
end
|
else
|
else
|
begin
|
begin
|
state <= state_typ_s_pad;
|
state <= state_typ_s_pad;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
state_typ_s_data:
|
state_typ_s_data:
|
begin
|
begin
|
if (count >= ilen - 1'b 1)
|
if (count >= ilen - 1'b 1)
|
begin
|
begin
|
process_11_cnttmp = 1'b 0;
|
process_11_cnttmp = 1'b 0;
|
if (data_only == 1'b 1)
|
if (data_only == 1'b 1)
|
begin
|
begin
|
// no PAD and no CRC ?
|
// no PAD and no CRC ?
|
state <= state_typ_s_idle;
|
state <= state_typ_s_idle;
|
end
|
end
|
else if (poscnt < 6'b 111100 - 1'b 1 )
|
else if (poscnt < 6'b 111100 - 1'b 1 )
|
begin
|
begin
|
// expect padding ?
|
// expect padding ?
|
state <= state_typ_s_pad;
|
state <= state_typ_s_pad;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
state <= state_typ_s_crc;
|
state <= state_typ_s_crc;
|
end
|
end
|
end
|
end
|
end
|
end
|
state_typ_s_pad:
|
state_typ_s_pad:
|
begin
|
begin
|
if (poscnt >= 6'b 111100 - 1'b 1)
|
if (poscnt >= 6'b 111100 - 1'b 1)
|
begin
|
begin
|
state <= state_typ_s_crc;
|
state <= state_typ_s_crc;
|
process_11_cnttmp = 1'b 0;
|
process_11_cnttmp = 1'b 0;
|
end
|
end
|
end
|
end
|
state_typ_s_crc:
|
state_typ_s_crc:
|
begin
|
begin
|
if (count >= 3)
|
if (count >= 3)
|
begin
|
begin
|
state <= state_typ_s_idle;
|
state <= state_typ_s_idle;
|
process_11_cnttmp = 1'b 0;
|
process_11_cnttmp = 1'b 0;
|
end
|
end
|
end
|
end
|
state_typ_s_utype:
|
state_typ_s_utype:
|
begin
|
begin
|
if (tx_dv == 1'b 0)
|
if (tx_dv == 1'b 0)
|
begin
|
begin
|
// unknown type... wait for end of frame
|
// unknown type... wait for end of frame
|
state <= state_typ_s_idle;
|
state <= state_typ_s_idle;
|
process_11_cnttmp = 1'b 0;
|
process_11_cnttmp = 1'b 0;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
// abort
|
// abort
|
// load the counter with the new value
|
// load the counter with the new value
|
count <= process_11_cnttmp;
|
count <= process_11_cnttmp;
|
end
|
end
|
end
|
end
|
|
|
// port signals internally reused
|
// port signals internally reused
|
|
|
endmodule // module ethmonitor_32
|
endmodule // module ethmonitor_32
|
|
|
|
|
