// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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//
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//
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// Revision Control Information
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// Revision Control Information
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//
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//
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// $RCSfile: timing_adapter_fifo_32.v,v $
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// $RCSfile: timing_adapter_fifo_32.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/gen/timing_adapter_fifo_32.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/gen/timing_adapter_fifo_32.v,v $
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//
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//
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// $Revision: #1 $
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// $Revision: #1 $
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// $Date: 2011/11/10 $
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// $Date: 2012/06/21 $
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// Check in by : $Author: max $
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// Check in by : $Author: swbranch $
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// Author : SKNg/TTChong
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// Author : SKNg/TTChong
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//
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//
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// Project : Triple Speed Ethernet - 10/100/1000 MAC
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// Project : Triple Speed Ethernet - 10/100/1000 MAC
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//
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//
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// Description : (Simulation only)
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// Description : (Simulation only)
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//
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//
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// Timing adapter FIFO
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// Timing adapter FIFO
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//
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//
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//
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//
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// ALTERA Confidential and Proprietary
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// ALTERA Confidential and Proprietary
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// Copyright 2006 (c) Altera Corporation
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// Copyright 2006 (c) Altera Corporation
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// All rights reserved
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// All rights reserved
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//
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//
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// --------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------
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// | simple_atlantic_fifo
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// | simple_atlantic_fifo
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// --------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module timing_adapter_fifo_32 (
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module timing_adapter_fifo_32 (
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output reg [ 3: 0] fill_level ,
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output reg [ 3: 0] fill_level ,
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// Interface: clock
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// Interface: clock
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input clk,
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input clk,
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input reset,
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input reset,
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// Interface: data_in
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// Interface: data_in
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output reg in_ready,
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output reg in_ready,
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input in_valid,
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input in_valid,
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input [36: 0] in_data,
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input [36: 0] in_data,
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// Interface: data_out
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// Interface: data_out
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input out_ready,
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input out_ready,
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output reg out_valid,
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output reg out_valid,
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output reg [36: 0] out_data
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output reg [36: 0] out_data
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);
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);
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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//| Internal Parameters
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//| Internal Parameters
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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parameter DEPTH = 8;
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parameter DEPTH = 8;
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parameter DATA_WIDTH = 37;
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parameter DATA_WIDTH = 37;
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parameter ADDR_WIDTH = 3;
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parameter ADDR_WIDTH = 3;
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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//| Signals
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//| Signals
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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reg [ADDR_WIDTH-1:0] wr_addr;
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reg [ADDR_WIDTH-1:0] wr_addr;
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reg [ADDR_WIDTH-1:0] rd_addr;
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reg [ADDR_WIDTH-1:0] rd_addr;
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reg [ADDR_WIDTH-1:0] next_wr_addr;
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reg [ADDR_WIDTH-1:0] next_wr_addr;
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reg [ADDR_WIDTH-1:0] next_rd_addr;
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reg [ADDR_WIDTH-1:0] next_rd_addr;
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reg [ADDR_WIDTH-1:0] mem_rd_addr;
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reg [ADDR_WIDTH-1:0] mem_rd_addr;
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reg [DATA_WIDTH-1:0] mem[DEPTH-1:0];
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reg [DATA_WIDTH-1:0] mem[DEPTH-1:0];
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reg empty;
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reg empty;
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reg full;
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reg full;
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reg out_ready_vector;
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reg out_ready_vector;
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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//| FIFO Status
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//| FIFO Status
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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always @(out_ready or wr_addr or rd_addr or full)
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always @(out_ready or wr_addr or rd_addr or full)
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begin
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begin
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// out_valid = !empty;
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// out_valid = !empty;
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out_ready_vector = out_ready;
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out_ready_vector = out_ready;
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in_ready = !full;
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in_ready = !full;
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next_wr_addr = wr_addr + 1;
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next_wr_addr = wr_addr + 1;
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next_rd_addr = rd_addr + 1;
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next_rd_addr = rd_addr + 1;
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fill_level[ADDR_WIDTH-1:0] = wr_addr - rd_addr;
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fill_level[ADDR_WIDTH-1:0] = wr_addr - rd_addr;
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fill_level[ADDR_WIDTH] = 0;
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fill_level[ADDR_WIDTH] = 0;
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if (full)
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if (full)
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fill_level = DEPTH;
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fill_level = DEPTH;
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end
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end
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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//| Manage Pointers
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//| Manage Pointers
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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always @ (posedge reset or posedge clk)
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always @ (posedge reset or posedge clk)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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wr_addr <= 0;
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wr_addr <= 0;
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rd_addr <= 0;
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rd_addr <= 0;
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empty <= 1;
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empty <= 1;
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rd_addr <= 0;
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rd_addr <= 0;
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full <= 0;
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full <= 0;
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out_valid<= 0;
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out_valid<= 0;
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end
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end
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else
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else
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begin
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begin
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out_valid <= !empty;
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out_valid <= !empty;
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if (in_ready && in_valid)
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if (in_ready && in_valid)
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begin
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begin
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wr_addr <= next_wr_addr;
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wr_addr <= next_wr_addr;
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empty <= 0;
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empty <= 0;
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if (next_wr_addr == rd_addr)
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if (next_wr_addr == rd_addr)
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full <= 1;
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full <= 1;
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end
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end
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if (out_ready_vector && out_valid)
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if (out_ready_vector && out_valid)
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begin
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begin
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rd_addr <= next_rd_addr;
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rd_addr <= next_rd_addr;
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full <= 0;
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full <= 0;
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if (next_rd_addr == wr_addr)
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if (next_rd_addr == wr_addr)
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begin
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begin
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empty <= 1;
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empty <= 1;
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out_valid <= 0;
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out_valid <= 0;
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end
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end
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end
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end
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if (out_ready_vector && out_valid && in_ready && in_valid)
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if (out_ready_vector && out_valid && in_ready && in_valid)
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begin
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begin
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full <= full;
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full <= full;
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empty <= empty;
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empty <= empty;
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end
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end
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end
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end
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end // always @ (posedge reset, posedge clk)
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end // always @ (posedge reset, posedge clk)
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always @ (rd_addr or out_ready or out_valid or next_rd_addr)
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always @ (rd_addr or out_ready or out_valid or next_rd_addr)
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begin
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begin
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mem_rd_addr = rd_addr;
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mem_rd_addr = rd_addr;
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if (out_ready && out_valid)
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if (out_ready && out_valid)
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begin
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begin
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mem_rd_addr = next_rd_addr;
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mem_rd_addr = next_rd_addr;
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end
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end
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end
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end
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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//| Infer Memory
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//| Infer Memory
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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always @ (posedge reset or posedge clk)
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always @ (posedge reset or posedge clk)
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begin
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begin
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if (reset)
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if (reset)
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mem[0] <= 38'h0;
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mem[0] <= 38'h0;
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else
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else
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begin
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begin
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if (in_ready && in_valid)
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if (in_ready && in_valid)
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mem[wr_addr] <= in_data;
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mem[wr_addr] <= in_data;
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end
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end
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out_data = mem[mem_rd_addr];
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out_data = mem[mem_rd_addr];
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end
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end
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endmodule //
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endmodule //
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