// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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//
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//
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// Revision Control Information
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// Revision Control Information
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//
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//
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// $RCSfile: top_ethgen32.v,v $
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// $RCSfile: top_ethgen32.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/gen/top_ethgen8.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/gen/top_ethgen8.v,v $
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//
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//
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// $Revision: #1 $
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// $Revision: #1 $
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// $Date: 2011/11/10 $
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// $Date: 2012/06/21 $
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// Check in by : $Author: max $
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// Check in by : $Author: swbranch $
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// Author : SKNg/TTChong
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// Author : SKNg/TTChong
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//
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//
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// Project : Triple Speed Ethernet - 10/100/1000 MAC
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// Project : Triple Speed Ethernet - 10/100/1000 MAC
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//
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//
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// Description : (Simulation only)
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// Description : (Simulation only)
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//
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//
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// Ethernet Traffic Generator for 8 bit fifoless MAC Atlantic client interface
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// Ethernet Traffic Generator for 8 bit fifoless MAC Atlantic client interface
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// Instantiates VERILOG module: ethgenerator (ethgen.v)
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// Instantiates VERILOG module: ethgenerator (ethgen.v)
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//
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//
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// ALTERA Confidential and Proprietary
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// ALTERA Confidential and Proprietary
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// Copyright 2006 (c) Altera Corporation
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// Copyright 2006 (c) Altera Corporation
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// All rights reserved
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// All rights reserved
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//
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//
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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`timescale 1 ns / 10 ps // timescale for following modules
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`timescale 1 ns / 10 ps // timescale for following modules
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module top_ethgenerator_8 (
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module top_ethgenerator_8 (
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reset,
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reset,
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clk,
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clk,
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enable,
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enable,
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dout,
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dout,
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dval,
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dval,
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derror,
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derror,
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sop,
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sop,
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eop,
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eop,
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mac_reverse,
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mac_reverse,
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dst,
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dst,
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src,
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src,
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prmble_len,
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prmble_len,
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pquant,
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pquant,
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vlan_ctl,
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vlan_ctl,
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len,
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len,
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frmtype,
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frmtype,
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cntstart,
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cntstart,
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cntstep,
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cntstep,
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ipg_len,
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ipg_len,
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payload_err,
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payload_err,
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prmbl_err,
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prmbl_err,
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crc_err,
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crc_err,
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vlan_en,
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vlan_en,
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stack_vlan,
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stack_vlan,
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pause_gen,
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pause_gen,
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pad_en,
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pad_en,
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phy_err,
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phy_err,
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end_err,
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end_err,
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data_only,
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data_only,
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start,
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start,
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done);
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done);
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parameter thold = 1.0 ;
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parameter thold = 1.0 ;
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parameter ZERO_LATENCY = 0;
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parameter ZERO_LATENCY = 0;
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parameter ENABLE_SHIFT16 = 1'b 0;
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parameter ENABLE_SHIFT16 = 1'b 0;
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input reset; // active high
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input reset; // active high
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input clk;
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input clk;
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input enable;
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input enable;
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output [7:0] dout;
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output [7:0] dout;
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output dval;
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output dval;
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output derror;
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output derror;
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output sop; // pulse with first word
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output sop; // pulse with first word
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output eop; // pulse with last word (tmod valid)
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output eop; // pulse with last word (tmod valid)
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input mac_reverse; // 1: dst/src are sent MSB first (non-standard)
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input mac_reverse; // 1: dst/src are sent MSB first (non-standard)
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input [47:0] dst; // destination address
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input [47:0] dst; // destination address
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input [47:0] src; // source address
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input [47:0] src; // source address
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input [3:0] prmble_len; // length of preamble
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input [3:0] prmble_len; // length of preamble
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input [15:0] pquant; // Pause Quanta value
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input [15:0] pquant; // Pause Quanta value
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input [15:0] vlan_ctl; // VLAN control info
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input [15:0] vlan_ctl; // VLAN control info
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input [15:0] len; // Length of payload
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input [15:0] len; // Length of payload
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input [15:0] frmtype; // if non-null: type field instead length
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input [15:0] frmtype; // if non-null: type field instead length
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input [7:0] cntstart; // payload data counter start (first byte of payload)
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input [7:0] cntstart; // payload data counter start (first byte of payload)
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input [7:0] cntstep; // payload counter step (2nd byte in paylaod)
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input [7:0] cntstep; // payload counter step (2nd byte in paylaod)
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input [15:0] ipg_len;
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input [15:0] ipg_len;
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input payload_err; // generate payload pattern error (last payload byte is wrong)
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input payload_err; // generate payload pattern error (last payload byte is wrong)
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input prmbl_err; // Send corrupt SFD in otherwise correct preamble
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input prmbl_err; // Send corrupt SFD in otherwise correct preamble
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input crc_err;
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input crc_err;
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input vlan_en;
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input vlan_en;
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input stack_vlan;
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input stack_vlan;
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input pause_gen;
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input pause_gen;
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input pad_en;
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input pad_en;
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input phy_err; // Generate the well known ERROR control character
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input phy_err; // Generate the well known ERROR control character
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input end_err; // Send corrupt TERMINATE character (wrong code)
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input end_err; // Send corrupt TERMINATE character (wrong code)
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input data_only; // if set omits preamble, padding, CRC
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input data_only; // if set omits preamble, padding, CRC
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input start;
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input start;
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output done;
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output done;
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wire [7:0] dout;
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wire [7:0] dout;
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reg [7:0] dout_reg;
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reg [7:0] dout_reg;
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wire dval;
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wire dval;
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reg dval_reg;
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reg dval_reg;
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wire derror;
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wire derror;
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reg derror_reg;
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reg derror_reg;
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wire sop;
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wire sop;
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wire eop;
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wire eop;
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// Frame Contents definitions
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// Frame Contents definitions
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wire done;
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wire done;
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reg done_reg;
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reg done_reg;
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// internal GMII from generator
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// internal GMII from generator
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wire [7:0] rxd;
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wire [7:0] rxd;
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wire rx_dv;
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wire rx_dv;
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wire rx_er;
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wire rx_er;
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wire sop_gen;
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wire sop_gen;
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wire eop_gen;
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wire eop_gen;
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reg start_gen;
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reg start_gen;
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wire done_gen;
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wire done_gen;
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// captured signals from generator (lasting 1 word clock cycle)
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// captured signals from generator (lasting 1 word clock cycle)
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wire enable_int;
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wire enable_int;
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reg enable_reg;
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reg enable_reg;
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reg sop_int; // captured sop_gen
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reg sop_int; // captured sop_gen
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wire sop_int_d; // captured sop_gen
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wire sop_int_d; // captured sop_gen
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reg eop_int; // captured eop_gen
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reg eop_int; // captured eop_gen
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wire eop_i; // captured eop_gen
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wire eop_i; // captured eop_gen
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reg rx_er_int; // captured rx_er
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reg rx_er_int; // captured rx_er
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// external signals
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// external signals
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reg sop_ex;
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reg sop_ex;
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reg eop_ex;
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reg eop_ex;
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// captured command signals
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// captured command signals
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reg [15:0] ipg_len_i;
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reg [15:0] ipg_len_i;
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// internal
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// internal
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reg [7:0] data8;
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reg [7:0] data8;
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wire [2:0] clkcnt;
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wire [2:0] clkcnt;
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reg [1:0] bytecnt_eop; // captured count for last word
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reg [1:0] bytecnt_eop; // captured count for last word
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integer count;
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integer count;
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//assign output
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//assign output
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reg [7:0] dout_temp;
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reg [7:0] dout_temp;
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reg dval_temp;
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reg dval_temp;
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reg derror_temp;
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reg derror_temp;
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reg sop_temp;
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reg sop_temp;
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reg eop_temp;
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reg eop_temp;
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reg done_temp;
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reg done_temp;
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reg [7:0] dout_before_delay;
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reg [7:0] dout_before_delay;
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reg dval_before_delay;
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reg dval_before_delay;
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reg derror_before_delay;
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reg derror_before_delay;
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reg sop_before_delay;
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reg sop_before_delay;
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reg eop_before_delay;
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reg eop_before_delay;
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reg done_before_delay;
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reg done_before_delay;
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// TYPE stm_typ:
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// TYPE stm_typ:
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parameter stm_typ_s_idle = 0;
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parameter stm_typ_s_idle = 0;
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parameter stm_typ_s_data = 1;
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parameter stm_typ_s_data = 1;
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parameter stm_typ_s_ipg = 2;
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parameter stm_typ_s_ipg = 2;
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parameter stm_typ_s_ipg0 = 3;
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parameter stm_typ_s_ipg0 = 3;
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parameter stm_typ_s_wait = 4;
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parameter stm_typ_s_wait = 4;
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reg [2:0] state;
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reg [2:0] state;
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reg clk_d;
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reg clk_d;
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reg fast_clk;
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reg fast_clk;
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reg fast_clk_gate;
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reg fast_clk_gate;
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reg [1:0] bytecnt;
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reg [1:0] bytecnt;
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reg tx_clk;
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reg tx_clk;
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// ---------------------------------------
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// ---------------------------------------
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// Generate internal fast clock synchronized to external input clock
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// Generate internal fast clock synchronized to external input clock
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// ---------------------------------------
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// ---------------------------------------
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always
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always
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begin : process_1
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begin : process_1
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fast_clk <= #(0.1) 1'b 0;
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fast_clk <= #(0.1) 1'b 0;
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#( 0.4 );
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#( 0.4 );
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fast_clk <= #(0.1) 1'b 1;
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fast_clk <= #(0.1) 1'b 1;
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#( 0.4 );
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#( 0.4 );
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end
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end
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always @(negedge fast_clk or posedge reset)
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always @(negedge fast_clk or posedge reset)
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begin : process_2
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begin : process_2
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if (reset == 1'b 1)
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if (reset == 1'b 1)
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begin
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begin
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fast_clk_gate <= 1'b 0;
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fast_clk_gate <= 1'b 0;
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clk_d <= 1'b 0;
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clk_d <= 1'b 0;
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end
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end
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else
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else
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begin
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begin
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// work on neg edge
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// work on neg edge
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clk_d <= clk;
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clk_d <= clk;
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if ((rx_dv == 1'b 0 | done_gen == 1'b 1) &
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if ((rx_dv == 1'b 0 | done_gen == 1'b 1) &
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(enable_int == 1'b 1 | start_gen == 1'b 1))
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(enable_int == 1'b 1 | start_gen == 1'b 1))
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begin
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begin
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// generator not running, enable it permanently
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// generator not running, enable it permanently
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fast_clk_gate <= 1'b 1;
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fast_clk_gate <= 1'b 1;
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end
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end
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else if (clk_d == 1'b 0 & clk == 1'b 1 &
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else if (clk_d == 1'b 0 & clk == 1'b 1 &
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state != stm_typ_s_wait & (enable_int == 1'b 1 |
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state != stm_typ_s_wait & (enable_int == 1'b 1 |
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state == stm_typ_s_ipg0) )
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state == stm_typ_s_ipg0) )
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begin
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begin
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// wait for rising edge
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// wait for rising edge
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fast_clk_gate <= 1'b 1;
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fast_clk_gate <= 1'b 1;
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end
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end
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else
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else
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begin
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begin
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fast_clk_gate <= 1'b 0;
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fast_clk_gate <= 1'b 0;
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end
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end
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end
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end
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end
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end
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// DDR process to generate gated clock
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// DDR process to generate gated clock
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always @(fast_clk or reset)
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always @(fast_clk or reset)
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begin : process_3
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begin : process_3
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if (reset == 1'b 1)
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if (reset == 1'b 1)
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begin
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begin
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tx_clk <= 1'b 0;
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tx_clk <= 1'b 0;
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end
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end
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else if ( fast_clk == 1'b 1 )
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else if ( fast_clk == 1'b 1 )
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begin
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begin
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if (fast_clk_gate == 1'b 1)
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if (fast_clk_gate == 1'b 1)
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begin
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begin
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tx_clk <= 1'b 1;
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tx_clk <= 1'b 1;
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end
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end
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end
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end
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else if ( fast_clk == 1'b 0 )
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else if ( fast_clk == 1'b 0 )
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begin
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begin
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tx_clk <= 1'b 0;
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tx_clk <= 1'b 0;
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end
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end
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end
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end
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// tx_clk <= fast_clk and fast_clk_gate;
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// tx_clk <= fast_clk and fast_clk_gate;
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// capture generator signals with word clock domain handshake
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// capture generator signals with word clock domain handshake
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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always @(posedge tx_clk or posedge reset)
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always @(posedge tx_clk or posedge reset)
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begin : process_4
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begin : process_4
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if (reset == 1'b 1)
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if (reset == 1'b 1)
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begin
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begin
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eop_int <= 1'b 0;
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eop_int <= 1'b 0;
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sop_int <= 1'b 0;
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sop_int <= 1'b 0;
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rx_er_int <= 1'b 0;
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rx_er_int <= 1'b 0;
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end
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end
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else
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else
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begin
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begin
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if (sop_gen == 1'b 1)
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if (sop_gen == 1'b 1)
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begin
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begin
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sop_int <= 1'b 1;
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sop_int <= 1'b 1;
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end
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end
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else if (sop_ex == 1'b 1 )
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else if (sop_ex == 1'b 1 )
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begin
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begin
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sop_int <= 1'b 0;
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sop_int <= 1'b 0;
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end
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end
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if (eop_gen == 1'b 1)
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if (eop_gen == 1'b 1)
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begin
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begin
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eop_int <= 1'b 1;
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eop_int <= 1'b 1;
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end
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end
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else if (eop_ex == 1'b 1 )
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else if (eop_ex == 1'b 1 )
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begin
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begin
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eop_int <= 1'b 0;
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eop_int <= 1'b 0;
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end
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end
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if (rx_er == 1'b 1)
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if (rx_er == 1'b 1)
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begin
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begin
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rx_er_int <= 1'b 1;
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rx_er_int <= 1'b 1;
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end
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end
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else if (eop_ex == 1'b 1 )
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else if (eop_ex == 1'b 1 )
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begin
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begin
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rx_er_int <= 1'b 0;
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rx_er_int <= 1'b 0;
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end
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end
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end
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end
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end
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end
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// word clock, external signal generation
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// word clock, external signal generation
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// --------------------------------------
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// --------------------------------------
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//assign #(thold) sop = sop_ex;
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//assign #(thold) sop = sop_ex;
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//assign #(thold) eop = eop_ex;
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//assign #(thold) eop = eop_ex;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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begin : process_5
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begin : process_5
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if (reset == 1'b 1)
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if (reset == 1'b 1)
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begin
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begin
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// enable_int <= 1'b 0;
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// enable_int <= 1'b 0;
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eop_ex <= 1'b 0;
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eop_ex <= 1'b 0;
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sop_ex <= 1'b 0;
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sop_ex <= 1'b 0;
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dval_reg <= 1'b 0;
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dval_reg <= 1'b 0;
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dout_reg <= {8{1'b 0}};
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dout_reg <= {8{1'b 0}};
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derror_reg <= 1'b 0;
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derror_reg <= 1'b 0;
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start_gen <= 1'b 0;
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start_gen <= 1'b 0;
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ipg_len_i <= 0;
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ipg_len_i <= 0;
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done_reg <= 1'b 0;
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done_reg <= 1'b 0;
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end
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end
|
else
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else
|
begin
|
begin
|
eop_ex <= eop_int;
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eop_ex <= eop_int;
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sop_ex <= sop_int;
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sop_ex <= sop_int;
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dout_reg <= #(thold) data8;
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dout_reg <= #(thold) data8;
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derror_reg <= #(thold) rx_er_int;
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derror_reg <= #(thold) rx_er_int;
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// enable_int <= enable;
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// enable_int <= enable;
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if (done_gen == 1'b 1 & enable_int == 1'b 1 &
|
if (done_gen == 1'b 1 & enable_int == 1'b 1 &
|
(state == stm_typ_s_idle | state == stm_typ_s_ipg0 |
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(state == stm_typ_s_idle | state == stm_typ_s_ipg0 |
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state == stm_typ_s_data & eop_int == 1'b 1 &
|
state == stm_typ_s_data & eop_int == 1'b 1 &
|
ipg_len_i < 4 & start == 1'b 1))
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ipg_len_i < 4 & start == 1'b 1))
|
begin
|
begin
|
// nextstate=S_IPG0
|
// nextstate=S_IPG0
|
start_gen <= start;
|
start_gen <= start;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
start_gen <= 1'b 0;
|
start_gen <= 1'b 0;
|
end
|
end
|
if ((state == stm_typ_s_data | state == stm_typ_s_ipg0) &
|
if ((state == stm_typ_s_data | state == stm_typ_s_ipg0) &
|
enable_int == 1'b 1 )//| start_gen == 1'b 1)
|
enable_int == 1'b 1 )//| start_gen == 1'b 1)
|
begin
|
begin
|
dval_reg <= #(thold) 1'b 1;
|
dval_reg <= #(thold) 1'b 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
dval_reg <= #(thold) 1'b 0;
|
dval_reg <= #(thold) 1'b 0;
|
end
|
end
|
// store input variables that could change until end of frame
|
// store input variables that could change until end of frame
|
if (sop_int == 1'b 1)
|
if (sop_int == 1'b 1)
|
begin
|
begin
|
ipg_len_i <= ipg_len;
|
ipg_len_i <= ipg_len;
|
end
|
end
|
// output last word modulo during eop
|
// output last word modulo during eop
|
// if (eop_int == 1'b 1)
|
// if (eop_int == 1'b 1)
|
// begin
|
// begin
|
// tmod_reg <= #(thold) bytecnt_eop;
|
// tmod_reg <= #(thold) bytecnt_eop;
|
// end
|
// end
|
// else if (eop_ex == 1'b 0 )
|
// else if (eop_ex == 1'b 0 )
|
// begin
|
// begin
|
// tmod_reg <= #(thold) {2{1'b 0}};
|
// tmod_reg <= #(thold) {2{1'b 0}};
|
// end
|
// end
|
done_reg <= done_gen;
|
done_reg <= done_gen;
|
end
|
end
|
end
|
end
|
// ------------------------
|
// ------------------------
|
// capture GMII data bytes
|
// capture GMII data bytes
|
// ------------------------
|
// ------------------------
|
always @(posedge tx_clk or posedge reset)
|
always @(posedge tx_clk or posedge reset)
|
begin : process_6
|
begin : process_6
|
if (reset == 1'b 1)
|
if (reset == 1'b 1)
|
begin
|
begin
|
data8 <= {8{1'b 0}};
|
data8 <= {8{1'b 0}};
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (sop_gen == 1'b 1 & rx_dv == 1'b 1)
|
if (sop_gen == 1'b 1 & rx_dv == 1'b 1)
|
begin
|
begin
|
// first byte
|
// first byte
|
data8 <= {rxd[7:0]};
|
data8 <= {rxd[7:0]};
|
end
|
end
|
else if (rx_dv == 1'b 1 )
|
else if (rx_dv == 1'b 1 )
|
begin
|
begin
|
// during frame
|
// during frame
|
data8 <= {rxd[7:0]};
|
data8 <= {rxd[7:0]};
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
// ------------------------
|
// ------------------------
|
// state machine
|
// state machine
|
// ------------------------
|
// ------------------------
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
begin : process_7
|
begin : process_7
|
if (reset == 1'b 1)
|
if (reset == 1'b 1)
|
begin
|
begin
|
state <= stm_typ_s_idle;
|
state <= stm_typ_s_idle;
|
count <= 8;
|
count <= 8;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (state == stm_typ_s_ipg)
|
if (state == stm_typ_s_ipg)
|
begin
|
begin
|
count <= count + 3'b 100;
|
count <= count + 3'b 100;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
count <= 8;
|
count <= 8;
|
end
|
end
|
case (state)
|
case (state)
|
stm_typ_s_idle:
|
stm_typ_s_idle:
|
begin
|
begin
|
if (done_gen == 1'b 0) // has the generator been triggered ?
|
if (done_gen == 1'b 0) // has the generator been triggered ?
|
begin
|
begin
|
state <= stm_typ_s_data;
|
state <= stm_typ_s_data;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
state <= stm_typ_s_idle;
|
state <= stm_typ_s_idle;
|
end
|
end
|
end
|
end
|
stm_typ_s_data:
|
stm_typ_s_data:
|
begin
|
begin
|
if (eop_int == 1'b 0 & enable_int == 1'b 1)
|
if (eop_int == 1'b 0 & enable_int == 1'b 1)
|
begin
|
begin
|
state <= stm_typ_s_data;
|
state <= stm_typ_s_data;
|
end
|
end
|
else if (eop_int == 1'b 0 & enable_int == 1'b 0 )
|
else if (eop_int == 1'b 0 & enable_int == 1'b 0 )
|
begin
|
begin
|
state <= stm_typ_s_wait;
|
state <= stm_typ_s_wait;
|
end
|
end
|
else if (eop_int == 1'b 1 )
|
else if (eop_int == 1'b 1 )
|
begin
|
begin
|
if (ipg_len_i < 4 & start == 1'b 1)
|
if (ipg_len_i < 4 & start == 1'b 1)
|
begin
|
begin
|
state <= stm_typ_s_ipg0; // no IPG
|
state <= stm_typ_s_ipg0; // no IPG
|
end
|
end
|
else if (ipg_len_i < 8 )
|
else if (ipg_len_i < 8 )
|
begin
|
begin
|
state <= stm_typ_s_idle;
|
state <= stm_typ_s_idle;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
state <= stm_typ_s_ipg;
|
state <= stm_typ_s_ipg;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
state <= stm_typ_s_data;
|
state <= stm_typ_s_data;
|
end
|
end
|
end
|
end
|
stm_typ_s_ipg:
|
stm_typ_s_ipg:
|
begin
|
begin
|
if (count < ipg_len_i)
|
if (count < ipg_len_i)
|
begin
|
begin
|
state <= stm_typ_s_ipg;
|
state <= stm_typ_s_ipg;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
state <= stm_typ_s_idle;
|
state <= stm_typ_s_idle;
|
end
|
end
|
end
|
end
|
stm_typ_s_ipg0:
|
stm_typ_s_ipg0:
|
begin
|
begin
|
state <= stm_typ_s_data;
|
state <= stm_typ_s_data;
|
end
|
end
|
stm_typ_s_wait:
|
stm_typ_s_wait:
|
begin
|
begin
|
if (enable_int == 1'b 1)
|
if (enable_int == 1'b 1)
|
begin
|
begin
|
state <= stm_typ_s_data;
|
state <= stm_typ_s_data;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
state <= stm_typ_s_wait;
|
state <= stm_typ_s_wait;
|
end
|
end
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
state <= stm_typ_s_idle;
|
state <= stm_typ_s_idle;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
begin
|
begin
|
if (reset == 1'b 1)
|
if (reset == 1'b 1)
|
begin
|
begin
|
dout_temp <= {8{1'b 0}};
|
dout_temp <= {8{1'b 0}};
|
dval_temp <= {{1'b 0}};
|
dval_temp <= {{1'b 0}};
|
derror_temp<= {{1'b 0}};
|
derror_temp<= {{1'b 0}};
|
sop_temp <= {{1'b 0}};
|
sop_temp <= {{1'b 0}};
|
eop_temp <= {{1'b 0}};
|
eop_temp <= {{1'b 0}};
|
done_temp <= 1'b 0;
|
done_temp <= 1'b 0;
|
|
|
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
dout_temp <= #(thold) dout_reg;
|
dout_temp <= #(thold) dout_reg;
|
dval_temp <= #(thold) dval_reg;
|
dval_temp <= #(thold) dval_reg;
|
derror_temp <= #(thold) derror_reg;
|
derror_temp <= #(thold) derror_reg;
|
sop_temp <= #(thold) sop_ex;
|
sop_temp <= #(thold) sop_ex;
|
eop_temp <= #(thold) eop_ex;
|
eop_temp <= #(thold) eop_ex;
|
done_temp <= #(thold) done_reg;
|
done_temp <= #(thold) done_reg;
|
end
|
end
|
end
|
end
|
|
|
generate if (ZERO_LATENCY == 1)
|
generate if (ZERO_LATENCY == 1)
|
begin
|
begin
|
timing_adapter_8 tb_adapter (
|
timing_adapter_8 tb_adapter (
|
|
|
// Interface: clk
|
// Interface: clk
|
.clk(clk), //input
|
.clk(clk), //input
|
.reset(reset), //input
|
.reset(reset), //input
|
// Interface: in
|
// Interface: in
|
.in_ready(enable_int), //output
|
.in_ready(enable_int), //output
|
.in_valid(dval_temp), //input
|
.in_valid(dval_temp), //input
|
.in_data(dout_temp), //input
|
.in_data(dout_temp), //input
|
.in_startofpacket(sop_temp), //input
|
.in_startofpacket(sop_temp), //input
|
.in_endofpacket(eop_temp), //input
|
.in_endofpacket(eop_temp), //input
|
.in_error({derror_temp}), //input
|
.in_error({derror_temp}), //input
|
// Interface: out
|
// Interface: out
|
.out_ready(enable), //input
|
.out_ready(enable), //input
|
.out_valid(dval), //output
|
.out_valid(dval), //output
|
.out_data(dout), //output
|
.out_data(dout), //output
|
.out_startofpacket(sop), //output
|
.out_startofpacket(sop), //output
|
.out_endofpacket(eop), //output
|
.out_endofpacket(eop), //output
|
.out_error({derror}) //output
|
.out_error({derror}) //output
|
|
|
);
|
);
|
|
|
assign done = done_temp;
|
assign done = done_temp;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
always @(posedge clk or posedge reset)
|
always @(posedge clk or posedge reset)
|
begin
|
begin
|
if (reset == 1'b 1)
|
if (reset == 1'b 1)
|
enable_reg <= 1'b 0;
|
enable_reg <= 1'b 0;
|
else
|
else
|
enable_reg <= enable;
|
enable_reg <= enable;
|
end
|
end
|
assign enable_int = enable_reg;
|
assign enable_int = enable_reg;
|
assign dout = dout_temp;
|
assign dout = dout_temp;
|
assign dval = dval_temp;
|
assign dval = dval_temp;
|
assign derror = derror_temp;
|
assign derror = derror_temp;
|
assign sop = sop_temp;
|
assign sop = sop_temp;
|
assign eop = eop_temp;
|
assign eop = eop_temp;
|
assign done = done_temp;
|
assign done = done_temp;
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
// Generator
|
// Generator
|
// ---------
|
// ---------
|
ethgenerator gen1g (
|
ethgenerator gen1g (
|
.reset(reset),
|
.reset(reset),
|
.rx_clk(tx_clk),
|
.rx_clk(tx_clk),
|
.enable(1'b1),
|
.enable(1'b1),
|
.rxd(rxd),
|
.rxd(rxd),
|
.rx_dv(rx_dv),
|
.rx_dv(rx_dv),
|
.rx_er(rx_er),
|
.rx_er(rx_er),
|
.sop(sop_gen),
|
.sop(sop_gen),
|
.eop(eop_gen),
|
.eop(eop_gen),
|
.mac_reverse(mac_reverse),
|
.mac_reverse(mac_reverse),
|
.dst(dst),
|
.dst(dst),
|
.src(src),
|
.src(src),
|
.prmble_len(prmble_len),
|
.prmble_len(prmble_len),
|
.pquant(pquant),
|
.pquant(pquant),
|
.vlan_ctl(vlan_ctl),
|
.vlan_ctl(vlan_ctl),
|
.len(len),
|
.len(len),
|
.frmtype(frmtype),
|
.frmtype(frmtype),
|
.cntstart(cntstart),
|
.cntstart(cntstart),
|
.cntstep(cntstep),
|
.cntstep(cntstep),
|
.ipg_len(16'h 4),
|
.ipg_len(16'h 4),
|
.payload_err(payload_err),
|
.payload_err(payload_err),
|
.prmbl_err(prmbl_err),
|
.prmbl_err(prmbl_err),
|
.crc_err(crc_err),
|
.crc_err(crc_err),
|
.vlan_en(vlan_en),
|
.vlan_en(vlan_en),
|
.stack_vlan(stack_vlan),
|
.stack_vlan(stack_vlan),
|
.pause_gen(pause_gen),
|
.pause_gen(pause_gen),
|
.pad_en(pad_en),
|
.pad_en(pad_en),
|
.phy_err(phy_err),
|
.phy_err(phy_err),
|
.end_err(end_err),
|
.end_err(end_err),
|
.data_only(data_only),
|
.data_only(data_only),
|
.runt_gen(1'b0) ,
|
.runt_gen(1'b0) ,
|
.long_pause(1'b0),
|
.long_pause(1'b0),
|
.carrier_sense(1'b0),
|
.carrier_sense(1'b0),
|
.false_carrier(1'b0),
|
.false_carrier(1'b0),
|
.carrier_extend(1'b0),
|
.carrier_extend(1'b0),
|
.carrier_extend_error(1'b0),
|
.carrier_extend_error(1'b0),
|
.start(start_gen),
|
.start(start_gen),
|
.done(done_gen));
|
.done(done_gen));
|
|
|
defparam gen1g.ENABLE_SHIFT16 = ENABLE_SHIFT16;
|
defparam gen1g.ENABLE_SHIFT16 = ENABLE_SHIFT16;
|
defparam gen1g.thold = 0.1;
|
defparam gen1g.thold = 0.1;
|
|
|
|
|
endmodule // module top_ethgenerator_8
|
endmodule // module top_ethgenerator_8
|
|
|
|
|
