/*
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/*
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Developed By Subtleware Corporation Pte Ltd 2011
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Developed By Subtleware Corporation Pte Ltd 2011
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File :
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File :
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Description :
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Description :
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Remarks :
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Remarks :
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Revision :
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Revision :
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Date Author Description
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Date Author Description
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02/09/12 Jefflieu
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02/09/12 Jefflieu
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*/
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*/
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`include "SGMIIDefs.v"
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`include "SGMIIDefs.v"
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module mReceive(
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module mReceive(
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input [07:00] i8_RxCodeGroupIn,
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input [07:00] i8_RxCodeGroupIn,
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input i_RxCodeInvalid,
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input i_RxCodeInvalid,
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input i_RxCodeCtrl,
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input i_RxCodeCtrl,
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input i_RxEven,
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input i_RxEven,
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input i_IsComma,
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input i_IsComma,
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input [02:00] i3_Xmit,
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input [02:00] i3_Xmit,
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input i_OrderedSetValid,
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input i_OrderedSetValid,
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input i_IsI1Set,
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input i_IsI1Set,
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input i_IsI2Set,
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input i_IsI2Set,
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input i_IsC1Set,
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input i_IsC1Set,
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input i_IsC2Set,
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input i_IsC2Set,
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input i_IsTSet,
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input i_IsTSet,
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input i_IsVSet,
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input i_IsVSet,
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input i_IsSSet,
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input i_IsSSet,
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input i_IsRSet,
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input i_IsRSet,
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input i_CheckEndKDK,
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input i_CheckEndKDK,
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input i_CheckEndKD21_5D0_0,
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input i_CheckEndKD21_5D0_0,
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input i_CheckEndKD2_2D0_0,
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input i_CheckEndKD2_2D0_0,
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input i_CheckEndTRK,
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input i_CheckEndTRK,
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input i_CheckEndTRR,
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input i_CheckEndTRR,
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input i_CheckEndRRR,
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input i_CheckEndRRR,
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input i_CheckEndRRK,
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input i_CheckEndRRK,
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input i_CheckEndRRS,
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input i_CheckEndRRS,
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output reg [15:00] o16_RxConfigReg,
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output reg [15:00] o16_RxConfigReg,
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output o_RUDIConfig,
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output o_RUDIConfig,
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output o_RUDIIdle,
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output o_RUDIIdle,
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output o_RUDIInvalid,
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output o_RUDIInvalid,
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output reg o_RxDV,
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output reg o_RxDV,
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output reg o_RxER,
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output reg o_RxER,
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output reg [07:00] o8_RxD,
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output reg [07:00] o8_RxD,
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output reg o_Invalid,
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output reg o_Invalid,
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output reg o_Receiving,
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output reg o_Receiving,
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input i_Clk,
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input i_Clk,
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input i_ARst_L
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input i_ARst_L
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);
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);
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localparam stWAIT_FOR_K = 21'h000001,
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localparam stWAIT_FOR_K = 21'h000001,
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stRX_K = 21'h000002,
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stRX_K = 21'h000002,
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stRX_CB = 21'h000004,
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stRX_CB = 21'h000004,
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stRX_CC = 21'h000008,
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stRX_CC = 21'h000008,
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stRX_CD = 21'h000010,
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stRX_CD = 21'h000010,
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stRX_INVALID = 21'h000020,
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stRX_INVALID = 21'h000020,
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stIDLE_D = 21'h000040,
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stIDLE_D = 21'h000040,
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stCARRIER_DTEC = 21'h000080,
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stFALSE_CARRIER = 21'h000080,
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stFALSE_CARRIER = 21'h000100,
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stSTART_OF_PKT = 21'h000100,
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stSTART_OF_PKT = 21'h000200,
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stEARLY_END = 21'h000200,
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stRECEIVE = 21'h000400,
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stTRI_RRI = 21'h000400,
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stEARLY_END = 21'h000800,
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stTRR_EXTEND = 21'h000800,
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stTRI_RRI = 21'h001000,
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stPKT_BURST_RRS = 21'h001000,
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stTRR_EXTEND = 21'h002000,
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stRX_DATA_ERR = 21'h002000,
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stEPD2_CHK_END = 21'h004000,
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stRX_DATA = 21'h004000,
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stPKT_BURST_RRS = 21'h008000,
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stEARLY_END_EXT = 21'h008000,
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stRX_DATA_ERR = 21'h010000,
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stEXT_ERROR = 21'h010000;
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stRX_DATA = 21'h020000,
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stEARLY_END_EXT = 21'h040000,
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stEXT_ERROR = 21'h080000,
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stLINK_FAILED = 21'h100000;
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reg [20:00] r21_State;
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reg [20:00] r21_NxtState;
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reg [16:00] r17_State;
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reg [16:00] r21_NxtState;
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wire wSUDIK28_5;
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wire wSUDIK28_5;
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wire wSUDID21_5;
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wire wSUDID21_5;
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wire wSUDID2_2;
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wire wSUDID2_2;
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wire wCarrierDtect;//what is this
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wire wCarrierDtect;//what is this
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wire wSUDI;
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wire wSUDI;
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wire w_IsC1Set;
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wire w_IsC1Set;
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wire w_IsC2Set;
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wire w_IsC2Set;
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wire w_IsI1Set;
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wire w_IsI1Set;
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wire w_IsI2Set;
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wire w_IsI2Set;
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wire w_IsRSet;
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wire w_IsRSet;
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wire w_IsSSet;
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wire w_IsSSet;
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wire w_IsTSet;
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wire w_IsTSet;
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wire w_IsVSet;
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wire w_IsVSet;
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//synthesis translate_off
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//synthesis translate_off
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reg [8*30-1:0] rvStateName;
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reg [8*30-1:0] rvStateName;
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always@(*)
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always@(*)
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begin
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begin
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case(r21_State)
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case(r17_State)
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stWAIT_FOR_K : rvStateName <= "Wait For K";
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stWAIT_FOR_K : rvStateName <= "Wait For K";
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stRX_K : rvStateName <= "RX K";
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stRX_K : rvStateName <= "RX K";
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stRX_CB : rvStateName <= "RX CB";
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stRX_CB : rvStateName <= "RX CB";
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stRX_CC : rvStateName <= "RX CC";
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stRX_CC : rvStateName <= "RX CC";
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stRX_CD : rvStateName <= "RX CD";
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stRX_CD : rvStateName <= "RX CD";
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stRX_INVALID : rvStateName <= "RX Invalid";
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stRX_INVALID : rvStateName <= "RX Invalid";
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stIDLE_D : rvStateName <= "IDLE D";
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stIDLE_D : rvStateName <= "IDLE D";
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stCARRIER_DTEC : rvStateName <= "CARRIER DETECT";
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//stCARRIER_DTEC : rvStateName <= "CARRIER DETECT";
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stFALSE_CARRIER : rvStateName <= "FALSE CARRIER";
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stFALSE_CARRIER : rvStateName <= "FALSE CARRIER";
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stSTART_OF_PKT : rvStateName <= "Start of Packet";
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stSTART_OF_PKT : rvStateName <= "Start of Packet";
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stRECEIVE : rvStateName <= "Receiving";
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//stRECEIVE : rvStateName <= "Receiving";
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stEARLY_END : rvStateName <= "Early End";
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stEARLY_END : rvStateName <= "Early End";
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stTRI_RRI : rvStateName <= "TRI RRI";
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stTRI_RRI : rvStateName <= "TRI RRI";
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stTRR_EXTEND : rvStateName <= "TRR Extend";
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stTRR_EXTEND : rvStateName <= "TRR Extend";
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stEPD2_CHK_END : rvStateName <= "EPD2 Check End";
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//stEPD2_CHK_END : rvStateName <= "EPD2 Check End";
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stPKT_BURST_RRS : rvStateName <= "PKT BURST RRS";
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stPKT_BURST_RRS : rvStateName <= "PKT BURST RRS";
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stRX_DATA_ERR : rvStateName <= "RX DATA Error";
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stRX_DATA_ERR : rvStateName <= "RX DATA Error";
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stRX_DATA : rvStateName <= "RX DATA";
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stRX_DATA : rvStateName <= "RX DATA";
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stEARLY_END_EXT : rvStateName <= "Early End Ext";
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stEARLY_END_EXT : rvStateName <= "Early End Ext";
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stEXT_ERROR : rvStateName <= "Ext Error";
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stEXT_ERROR : rvStateName <= "Ext Error";
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stLINK_FAILED : rvStateName <= "Link Failed";
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//stLINK_FAILED : rvStateName <= "Link Failed";
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endcase
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endcase
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//$display("mReceive State: %s",rvStateName);
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//$display("mReceive State: %s",rvStateName);
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end
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end
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//synthesis translate_on
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//synthesis translate_on
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assign w_IsSSet = i_OrderedSetValid && i_IsRSet;
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assign w_IsSSet = i_OrderedSetValid && i_IsRSet;
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assign wSUDI = ~i_RxCodeInvalid;
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assign wSUDI = ~i_RxCodeInvalid;
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assign wCarrierDtect = i_IsRSet|i_IsSSet|i_IsTSet|i_IsVSet;
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assign wCarrierDtect = i_IsRSet|i_IsSSet|i_IsTSet|i_IsVSet;
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always@(posedge i_Clk or negedge i_ARst_L)
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always@(posedge i_Clk or negedge i_ARst_L)
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if(i_ARst_L==1'b0) begin
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if(i_ARst_L==1'b0) begin
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r21_State <= stWAIT_FOR_K;
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r17_State <= stWAIT_FOR_K;
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end else begin
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end else begin
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r21_State <= r21_NxtState;
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r17_State <= r21_NxtState;
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end
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end
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assign wSUDIK28_5 = (!i_RxCodeInvalid) && (i_RxCodeCtrl) && (i8_RxCodeGroupIn==`K28_5);
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assign wSUDIK28_5 = (!i_RxCodeInvalid) && (i_RxCodeCtrl) && (i8_RxCodeGroupIn==`K28_5);
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assign wSUDID21_5 = (!i_RxCodeInvalid) && (!i_RxCodeCtrl) && (i8_RxCodeGroupIn==`D21_5);
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assign wSUDID21_5 = (!i_RxCodeInvalid) && (!i_RxCodeCtrl) && (i8_RxCodeGroupIn==`D21_5);
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assign wSUDID2_2 = (!i_RxCodeInvalid) && (!i_RxCodeCtrl) && (i8_RxCodeGroupIn==`D2_2);
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assign wSUDID2_2 = (!i_RxCodeInvalid) && (!i_RxCodeCtrl) && (i8_RxCodeGroupIn==`D2_2);
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always@(*)
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always@(*)
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begin
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begin
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case(r21_State)
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case(r17_State)
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stWAIT_FOR_K: if(i_IsComma && i_RxEven) r21_NxtState <= stRX_K; else r21_NxtState<=stWAIT_FOR_K;
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stWAIT_FOR_K: if(i_IsComma && i_RxEven) r21_NxtState <= stRX_K; else r21_NxtState<=stWAIT_FOR_K;
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stRX_K : if(wSUDID21_5||wSUDID2_2)
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stRX_K : if(wSUDID21_5||wSUDID2_2)
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r21_NxtState <= stRX_CB; else
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r21_NxtState <= stRX_CB; else
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if((!i_RxCodeInvalid) && (i_RxCodeCtrl) && i3_Xmit!=`cXmitDATA)
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if((!i_RxCodeInvalid) && (i_RxCodeCtrl) && i3_Xmit!=`cXmitDATA)
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r21_NxtState <= stRX_INVALID; else
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r21_NxtState <= stRX_INVALID; else
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if(((!i_RxCodeInvalid) && (!i_RxCodeCtrl) && i3_Xmit!=`cXmitDATA && i8_RxCodeGroupIn!=`D21_5 && i8_RxCodeGroupIn!=`D2_2)||
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if(((!i_RxCodeInvalid) && (!i_RxCodeCtrl) && i3_Xmit!=`cXmitDATA && i8_RxCodeGroupIn!=`D21_5 && i8_RxCodeGroupIn!=`D2_2)||
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((!i_RxCodeInvalid) && i3_Xmit==`cXmitDATA && ((i8_RxCodeGroupIn!=`D21_5 && i8_RxCodeGroupIn!=`D2_2 && (!i_RxCodeCtrl))||i_RxCodeCtrl)))
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((!i_RxCodeInvalid) && i3_Xmit==`cXmitDATA && ((i8_RxCodeGroupIn!=`D21_5 && i8_RxCodeGroupIn!=`D2_2 && (!i_RxCodeCtrl))||i_RxCodeCtrl)))
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r21_NxtState <= stIDLE_D; else
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r21_NxtState <= stIDLE_D; else
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r21_NxtState <= stRX_K;
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r21_NxtState <= stRX_K;
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stRX_CB : if((!i_RxCodeInvalid) && (!i_RxCodeCtrl)) r21_NxtState <= stRX_CC; else r21_NxtState <= stRX_INVALID;
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stRX_CB : if((!i_RxCodeInvalid) && (!i_RxCodeCtrl)) r21_NxtState <= stRX_CC; else r21_NxtState <= stRX_INVALID;
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stRX_CC : if((!i_RxCodeInvalid) && (!i_RxCodeCtrl)) r21_NxtState <= stRX_CD; else r21_NxtState <= stRX_INVALID;
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stRX_CC : if((!i_RxCodeInvalid) && (!i_RxCodeCtrl)) r21_NxtState <= stRX_CD; else r21_NxtState <= stRX_INVALID;
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stRX_CD : if((!i_RxCodeInvalid) && (i_RxCodeCtrl) && i8_RxCodeGroupIn==`K28_5 && i_RxEven)
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stRX_CD : if((!i_RxCodeInvalid) && (i_RxCodeCtrl) && i8_RxCodeGroupIn==`K28_5 && i_RxEven)
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r21_NxtState <= stRX_K;
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r21_NxtState <= stRX_K;
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else
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else
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r21_NxtState <= stRX_INVALID;
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r21_NxtState <= stRX_INVALID;
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stRX_INVALID: if(wSUDIK28_5 && i_RxEven)
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stRX_INVALID: if(wSUDIK28_5 && i_RxEven)
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r21_NxtState <= stRX_K;
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r21_NxtState <= stRX_K;
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else
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else
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r21_NxtState <= stWAIT_FOR_K;
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r21_NxtState <= stWAIT_FOR_K;
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stIDLE_D : if(!wSUDIK28_5 && (i3_Xmit!=`cXmitDATA))
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stIDLE_D : if(!wSUDIK28_5 && (i3_Xmit!=`cXmitDATA))
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r21_NxtState <= stRX_INVALID;
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r21_NxtState <= stRX_INVALID;
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else if(!i_RxCodeInvalid && i3_Xmit==`cXmitDATA && i_IsSSet)
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else if(!i_RxCodeInvalid && i3_Xmit==`cXmitDATA && i_IsSSet)
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r21_NxtState <= stSTART_OF_PKT;
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r21_NxtState <= stSTART_OF_PKT;
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else if((!i_RxCodeInvalid && i3_Xmit==`cXmitDATA && (~wCarrierDtect)) || (wSUDIK28_5 && i_RxEven))
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else if((!i_RxCodeInvalid && i3_Xmit==`cXmitDATA && (~wCarrierDtect)) || (wSUDIK28_5 && i_RxEven))
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r21_NxtState <= stRX_K;
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r21_NxtState <= stRX_K;
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else
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else
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r21_NxtState <= stFALSE_CARRIER;
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r21_NxtState <= stFALSE_CARRIER;
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/*stCARRIER_DTEC: if(i_OrderedSetValid && i_IsSSet)
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/*stCARRIER_DTEC: if(i_OrderedSetValid && i_IsSSet)
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r21_NxtState <= stSTART_OF_PKT;
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r21_NxtState <= stSTART_OF_PKT;
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else
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else
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r21_NxtState <= stFALSE_CARRIER;*/
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r21_NxtState <= stFALSE_CARRIER;*/
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stFALSE_CARRIER : if(wSUDIK28_5 && i_RxEven) r21_NxtState <= stRX_K; else r21_NxtState <= stFALSE_CARRIER;
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stFALSE_CARRIER : if(wSUDIK28_5 && i_RxEven) r21_NxtState <= stRX_K; else r21_NxtState <= stFALSE_CARRIER;
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stSTART_OF_PKT : if(wSUDI)
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stSTART_OF_PKT : if(wSUDI)
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begin
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begin
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if(~i_RxCodeCtrl) r21_NxtState <= stRX_DATA; else
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if(~i_RxCodeCtrl) r21_NxtState <= stRX_DATA; else
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if((i_CheckEndKDK||i_CheckEndKD21_5D0_0||i_CheckEndKD2_2D0_0) &&i_RxEven)
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if((i_CheckEndKDK||i_CheckEndKD21_5D0_0||i_CheckEndKD2_2D0_0) &&i_RxEven)
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r21_NxtState <= stEARLY_END; else
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r21_NxtState <= stEARLY_END; else
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if(i_CheckEndTRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
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if(i_CheckEndTRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
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if(i_CheckEndTRR) r21_NxtState <= stTRR_EXTEND; else
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if(i_CheckEndTRR) r21_NxtState <= stTRR_EXTEND; else
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if(i_CheckEndRRR) r21_NxtState <= stEARLY_END_EXT; else
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if(i_CheckEndRRR) r21_NxtState <= stEARLY_END_EXT; else
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r21_NxtState <= stRX_DATA_ERR;
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r21_NxtState <= stRX_DATA_ERR;
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end
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end
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else r21_NxtState <= stRX_DATA_ERR;
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else r21_NxtState <= stRX_DATA_ERR;
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//stRECEIVE : //zero cycle state
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//stRECEIVE : //zero cycle state
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stRX_DATA : if(wSUDI)
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stRX_DATA : if(wSUDI)
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begin
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begin
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if(~i_RxCodeCtrl) r21_NxtState <= stRX_DATA; else
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if(~i_RxCodeCtrl) r21_NxtState <= stRX_DATA; else
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if((i_CheckEndKDK||i_CheckEndKD21_5D0_0||i_CheckEndKD2_2D0_0) &&i_RxEven)
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if((i_CheckEndKDK||i_CheckEndKD21_5D0_0||i_CheckEndKD2_2D0_0) &&i_RxEven)
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r21_NxtState <= stEARLY_END; else
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r21_NxtState <= stEARLY_END; else
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if(i_CheckEndTRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
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if(i_CheckEndTRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
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if(i_CheckEndTRR) r21_NxtState <= stTRR_EXTEND; else
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if(i_CheckEndTRR) r21_NxtState <= stTRR_EXTEND; else
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if(i_CheckEndRRR) r21_NxtState <= stEARLY_END_EXT; else
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if(i_CheckEndRRR) r21_NxtState <= stEARLY_END_EXT; else
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r21_NxtState <= stRX_DATA_ERR;
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r21_NxtState <= stRX_DATA_ERR;
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end
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end
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else r21_NxtState <= stRX_DATA_ERR;
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else r21_NxtState <= stRX_DATA_ERR;
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stRX_DATA_ERR : if(wSUDI)
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stRX_DATA_ERR : if(wSUDI)
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begin
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begin
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if(~i_RxCodeCtrl) r21_NxtState <= stRX_DATA; else
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if(~i_RxCodeCtrl) r21_NxtState <= stRX_DATA; else
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if((i_CheckEndKDK||i_CheckEndKD21_5D0_0||i_CheckEndKD2_2D0_0) &&i_RxEven)
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if((i_CheckEndKDK||i_CheckEndKD21_5D0_0||i_CheckEndKD2_2D0_0) &&i_RxEven)
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r21_NxtState <= stEARLY_END; else
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r21_NxtState <= stEARLY_END; else
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if(i_CheckEndTRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
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if(i_CheckEndTRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
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if(i_CheckEndTRR) r21_NxtState <= stTRR_EXTEND; else
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if(i_CheckEndTRR) r21_NxtState <= stTRR_EXTEND; else
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if(i_CheckEndRRR) r21_NxtState <= stEARLY_END_EXT; else
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if(i_CheckEndRRR) r21_NxtState <= stEARLY_END_EXT; else
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r21_NxtState <= stRX_DATA_ERR;
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r21_NxtState <= stRX_DATA_ERR;
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end
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end
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else r21_NxtState <= stRX_DATA_ERR;
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else r21_NxtState <= stRX_DATA_ERR;
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stEARLY_END : if(wSUDID21_5||wSUDID2_2) r21_NxtState <= stRX_CB; else r21_NxtState <= stIDLE_D;
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stEARLY_END : if(wSUDID21_5||wSUDID2_2) r21_NxtState <= stRX_CB; else r21_NxtState <= stIDLE_D;
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stTRI_RRI : if(wSUDIK28_5) r21_NxtState <= stRX_K; else r21_NxtState <= stTRI_RRI;
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stTRI_RRI : if(wSUDIK28_5) r21_NxtState <= stRX_K; else r21_NxtState <= stTRI_RRI;
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stTRR_EXTEND : if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
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stTRR_EXTEND : if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
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if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
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if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
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if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
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if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
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if(i_IsVSet) r21_NxtState <= stEXT_ERROR; else
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if(i_IsVSet) r21_NxtState <= stEXT_ERROR; else
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r21_NxtState <= stTRR_EXTEND;
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r21_NxtState <= stTRR_EXTEND;
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stEARLY_END_EXT : if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
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stEARLY_END_EXT : if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
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if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
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if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
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if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
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if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
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if(i_IsVSet) r21_NxtState <= stEXT_ERROR; else
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if(i_IsVSet) r21_NxtState <= stEXT_ERROR; else
|
r21_NxtState <= stEARLY_END_EXT;
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r21_NxtState <= stEARLY_END_EXT;
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//This is zero cycle state
|
//This is zero cycle state
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//stEPD2_CHK_END : if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
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//stEPD2_CHK_END : if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
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// if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
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// if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
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// if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
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// if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
|
// r21_NxtState <= stEXT_ERROR;
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// r21_NxtState <= stEXT_ERROR;
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stPKT_BURST_RRS : if(i_IsSSet && i_OrderedSetValid && wSUDI) r21_NxtState <= stSTART_OF_PKT; else r21_NxtState <= stPKT_BURST_RRS;
|
stPKT_BURST_RRS : if(i_IsSSet && i_OrderedSetValid && wSUDI) r21_NxtState <= stSTART_OF_PKT; else r21_NxtState <= stPKT_BURST_RRS;
|
stEXT_ERROR : if(i_IsSSet && i_OrderedSetValid && wSUDI) r21_NxtState <= stSTART_OF_PKT; else
|
stEXT_ERROR : if(i_IsSSet && i_OrderedSetValid && wSUDI) r21_NxtState <= stSTART_OF_PKT; else
|
if(wSUDIK28_5 && i_RxEven) r21_NxtState <= stRX_K; else
|
if(wSUDIK28_5 && i_RxEven) r21_NxtState <= stRX_K; else
|
if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
|
if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
|
if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
|
if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
|
if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
|
if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
|
r21_NxtState <= stEXT_ERROR;
|
r21_NxtState <= stEXT_ERROR;
|
endcase
|
endcase
|
end
|
end
|
|
|
assign o_RUDIConfig = (r21_State==stRX_CD )?1'b1:1'b0;
|
assign o_RUDIConfig = (r17_State==stRX_CD )?1'b1:1'b0;
|
assign o_RUDIIdle = (r21_State==stIDLE_D )?1'b1:1'b0;
|
assign o_RUDIIdle = (r17_State==stIDLE_D )?1'b1:1'b0;
|
assign o_RUDIInvalid= (r21_State==stRX_INVALID && i3_Xmit==`cXmitCONFIG)?1'b1:1'b0;
|
assign o_RUDIInvalid= (r17_State==stRX_INVALID && i3_Xmit==`cXmitCONFIG)?1'b1:1'b0;
|
|
|
always@(posedge i_Clk or negedge i_ARst_L)
|
always@(posedge i_Clk or negedge i_ARst_L)
|
if(i_ARst_L==1'b0) begin
|
if(i_ARst_L==1'b0) begin
|
o_Receiving <= 1'b0;
|
o_Receiving <= 1'b0;
|
o_RxDV <= 1'b0;
|
o_RxDV <= 1'b0;
|
o_RxER <= 1'b0;
|
o_RxER <= 1'b0;
|
o8_RxD <= 8'h0;
|
o8_RxD <= 8'h0;
|
o16_RxConfigReg <= 16'h00;
|
o16_RxConfigReg <= 16'h00;
|
end else begin
|
end else begin
|
|
|
case(r21_NxtState)
|
case(r21_NxtState)
|
//stWAIT_FOR_K :
|
//stWAIT_FOR_K :
|
stRX_K : begin
|
stRX_K : begin
|
o_Receiving <= 1'b0;
|
o_Receiving <= 1'b0;
|
o_RxDV <= 1'b0;
|
o_RxDV <= 1'b0;
|
o_RxER <= 1'b0;
|
o_RxER <= 1'b0;
|
end
|
end
|
//stRX_CB :
|
//stRX_CB :
|
stRX_CC : o16_RxConfigReg[07:00] <= i8_RxCodeGroupIn;
|
stRX_CC : o16_RxConfigReg[07:00] <= i8_RxCodeGroupIn;
|
stRX_CD : o16_RxConfigReg[15:08] <= i8_RxCodeGroupIn;
|
stRX_CD : o16_RxConfigReg[15:08] <= i8_RxCodeGroupIn;
|
stRX_INVALID : if(i3_Xmit==`cXmitDATA) o_Receiving <= 1'b1;
|
stRX_INVALID : if(i3_Xmit==`cXmitDATA) o_Receiving <= 1'b1;
|
stIDLE_D : begin
|
stIDLE_D : begin
|
o_Receiving <= 1'b0;
|
o_Receiving <= 1'b0;
|
o_RxDV <= 1'b0;
|
o_RxDV <= 1'b0;
|
o_RxER <= 1'b0;
|
o_RxER <= 1'b0;
|
end
|
end
|
|
|
//stCARRIER_DTEC: o_Receiving <= 1'b1;
|
//stCARRIER_DTEC: o_Receiving <= 1'b1;
|
stFALSE_CARRIER : begin
|
stFALSE_CARRIER : begin
|
o_RxER <= 1'b1;
|
o_RxER <= 1'b1;
|
o8_RxD <= 8'h0E;
|
o8_RxD <= 8'h0E;
|
end
|
end
|
stSTART_OF_PKT : begin
|
stSTART_OF_PKT : begin
|
o_Receiving <= 1'b1;
|
o_Receiving <= 1'b1;
|
o_RxDV <= 1'b1;
|
o_RxDV <= 1'b1;
|
o_RxER <= 1'b0;
|
o_RxER <= 1'b0;
|
o8_RxD <= 8'h55;
|
o8_RxD <= 8'h55;
|
end
|
end
|
//stRECEIVE :
|
//stRECEIVE :
|
stEARLY_END : o_RxER <= 1'b1;
|
stEARLY_END : o_RxER <= 1'b1;
|
stTRI_RRI : begin
|
stTRI_RRI : begin
|
o_Receiving <= 1'b0;
|
o_Receiving <= 1'b0;
|
o_RxER <= 1'b0;
|
o_RxER <= 1'b0;
|
o_RxDV <= 1'b0;
|
o_RxDV <= 1'b0;
|
end
|
end
|
stTRR_EXTEND : begin
|
stTRR_EXTEND : begin
|
o_RxER <= 1'b1;
|
o_RxER <= 1'b1;
|
o_RxDV <= 1'b0;
|
o_RxDV <= 1'b0;
|
o8_RxD <= 8'h0F;
|
o8_RxD <= 8'h0F;
|
end
|
end
|
//stEPD2_CHK_END :
|
//stEPD2_CHK_END :
|
stPKT_BURST_RRS : begin
|
stPKT_BURST_RRS : begin
|
o_RxDV <= 1'b0;
|
o_RxDV <= 1'b0;
|
o8_RxD <= 8'b0000_1111;
|
o8_RxD <= 8'b0000_1111;
|
end
|
end
|
stRX_DATA_ERR : o_RxER <= 1'b1;
|
stRX_DATA_ERR : o_RxER <= 1'b1;
|
stRX_DATA : begin
|
stRX_DATA : begin
|
o_RxER <= 1'b0;
|
o_RxER <= 1'b0;
|
o8_RxD <= i8_RxCodeGroupIn;
|
o8_RxD <= i8_RxCodeGroupIn;
|
end
|
end
|
stEARLY_END_EXT : o_RxER <= 1'b1;
|
stEARLY_END_EXT : o_RxER <= 1'b1;
|
stEXT_ERROR : begin
|
stEXT_ERROR : begin
|
o_RxDV <= 1'b0;
|
o_RxDV <= 1'b0;
|
o8_RxD <= 8'b0001_1111;
|
o8_RxD <= 8'b0001_1111;
|
end
|
end
|
stLINK_FAILED : begin
|
// stLINK_FAILED : begin
|
if(o_Receiving==1'b1)
|
// if(o_Receiving==1'b1)
|
begin
|
// begin
|
o_Receiving <= 1'b0;
|
// o_Receiving <= 1'b0;
|
o_RxER <= 1'b1;
|
// o_RxER <= 1'b1;
|
end else
|
// end else
|
begin
|
// begin
|
o_RxDV <= 1'b0;
|
// o_RxDV <= 1'b0;
|
o_RxER <= 1'b0;
|
// o_RxER <= 1'b0;
|
end
|
// end
|
if(i3_Xmit!=`cXmitDATA) o_Invalid <= 1'b1;
|
// if(i3_Xmit!=`cXmitDATA) o_Invalid <= 1'b1;
|
end
|
// end
|
endcase
|
endcase
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
