/*
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/*
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Developed By Subtleware Corporation Pte Ltd 2011
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Developed By Subtleware Corporation Pte Ltd 2011
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File :
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File :
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Description :
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Description :
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Remarks :
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Remarks :
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Revision :
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Revision :
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Date Author Description
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Date Author Description
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02/09/12 Jefflieu
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02/09/12 Jefflieu
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*/
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*/
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`timescale 1ns/100ps
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`timescale 1ns/100ps
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`include "SGMIIDefs.v"
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`include "SGMIIDefs.v"
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module mRegisters(
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module mRegisters(
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input w_ARstLogic_L,
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input w_ARstLogic_L,
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input i_Clk,
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input i_Clk,
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input i_Cyc,
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input i_Cyc,
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input i_Stb,
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input i_Stb,
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input i_WEn,
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input i_WEn,
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input [07:00] i8_Addr,
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input [07:00] i8_Addr,
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input [31:00] i32_WrData,
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input [31:00] i32_WrData,
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output reg [31:00] o32_RdData,
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output reg [31:00] o32_RdData,
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output reg o_Ack,
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output reg o_Ack,
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output o_Stall,
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output o_Stall,
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inout io_Mdio,
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inout io_Mdio,
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input i_Mdc,
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input i_Mdc,
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//This is used in Phy-Side SGMII
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//This is used in Phy-Side SGMII
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input i_PhyLink,
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input i_PhyLink,
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input i_PhyDuplex,
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input i_PhyDuplex,
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input [1:0] i2_PhySpeed,
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input [1:0] i2_PhySpeed,
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//MAC-Side Speed,
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//MAC-Side Speed,
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output [01:00] o2_SGMIISpeed,
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output [01:00] o2_SGMIISpeed,
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//MAC-Side Duplex,
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//MAC-Side Duplex,
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output o_SGMIIDuplex,
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output o_SGMIIDuplex,
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//Register in and out,
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//Register in and out,
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output [20:00] o21_LinkTimer,
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output [20:00] o21_LinkTimer,
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input [02:00] i3_XmitState,
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input [02:00] i3_XmitState,
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input [15:00] i16_TxConfigReg,
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input [15:00] i16_TxConfigReg,
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output o_MIIRst_L,
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output o_MIIRst_L,
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output o_ANEnable,
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output o_ANEnable,
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output o_ANRestart,
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output o_ANRestart,
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output o_Loopback,
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output o_Loopback,
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output o_GXBPowerDown,
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output o_GXBPowerDown,
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output [15:00] o16_LcAdvAbility,
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output [15:00] o16_LcAdvAbility,
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input i_ANComplete,
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input i_ANComplete,
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input i_SyncStatus,
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input i_SyncStatus,
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input [15:00] i16_LpAdvAbility);
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input [15:00] i16_LpAdvAbility);
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//TODO: Local BUs interface to setup registers
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//TODO: Local BUs interface to setup registers
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//Register Write
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//Register Write
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wire w_Write;
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wire w_Write;
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reg r_Write;
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reg r_Write;
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wire w_WritePulse;
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wire w_WritePulse;
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wire [04:00] w5_Addr;
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wire [04:00] w5_Addr;
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wire [15:00] w16_WrData;
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wire [15:00] w16_WrData;
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reg [15:00] r16_CtrlReg0;
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reg [15:00] r16_CtrlReg0;
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reg [15:00] r16_CtrlReg4;
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reg [15:00] r16_CtrlReg4;
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wire [15:00] w16_StatusReg1;
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wire [15:00] w16_StatusReg1;
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reg [15:00] r16_ModeReg;
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reg [15:00] r16_ModeReg;
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wire [15:00] w16_LcAdvAbility;
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wire [15:00] w16_LcAdvAbility;
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wire w_UseAsSGMII;
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wire w_UseAsSGMII;
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reg r_Read;
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reg r_Read;
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wire w_Read;
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wire w_Read;
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wire w_ReadPulse;
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wire w_ReadPulse;
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wire w_SGMII_PHY;
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wire w_SGMII_PHY;
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reg [20:00] r21_LinkTimer;
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reg [20:00] r21_LinkTimer;
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reg [15:00] r16_ScratchRev;
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reg [15:00] r16_ScratchRev;
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wire w_UseLcConfig;
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wire w_UseLcConfig;
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assign o21_LinkTimer = r21_LinkTimer;
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assign o21_LinkTimer = r21_LinkTimer;
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assign w5_Addr = i8_Addr[6:2];
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assign w5_Addr = i8_Addr[6:2];
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assign w16_WrData = i32_WrData[15:00];
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assign w16_WrData = i32_WrData[15:00];
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assign w_Write = (i_Cyc & i_Stb & i_WEn);
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assign w_Write = (i_Cyc & i_Stb & i_WEn);
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assign w_WritePulse = w_Write & (~r_Write);
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assign w_WritePulse = w_Write & (~r_Write);
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assign w_Read = (i_Cyc & i_Stb & (~i_WEn));
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assign w_Read = (i_Cyc & i_Stb & (~i_WEn));
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assign w_ReadPulse = w_Read & (~r_Read);
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assign w_ReadPulse = w_Read & (~r_Read);
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assign o_Stall = (w_Write|w_Read)&(~o_Ack);
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assign o_Stall = (w_Write|w_Read)&(~o_Ack);
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always@(posedge i_Clk or negedge w_ARstLogic_L)
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always@(posedge i_Clk or negedge w_ARstLogic_L)
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if(w_ARstLogic_L==1'b0)
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if(w_ARstLogic_L==1'b0)
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begin
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begin
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r16_CtrlReg4 <= `cReg4Default;
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r16_CtrlReg4 <= `cReg4Default;
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r16_CtrlReg0 <= `cReg0Default;
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r16_CtrlReg0 <= `cReg0Default;
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r16_ModeReg <= `cRegXDefault;
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r16_ModeReg <= `cRegXDefault;
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r21_LinkTimer <= `cRegLinkTimerDefault;
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r21_LinkTimer <= `cRegLinkTimerDefault;
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r16_ScratchRev <= 16'h1_0_00;
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r16_ScratchRev <= 16'h1_0_00;
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end
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end
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else
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else
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begin
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begin
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//Write Controller
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//Write Controller
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r_Write <= w_Write;
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r_Write <= w_Write;
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o_Ack <= w_WritePulse|w_ReadPulse;
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o_Ack <= w_WritePulse|w_ReadPulse;
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//Control Register 0
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//Control Register 0
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if(w_WritePulse && w5_Addr==5'b00000) r16_CtrlReg0 <= w16_WrData;
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if(w_WritePulse && w5_Addr==5'b00000) r16_CtrlReg0 <= w16_WrData;
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else begin
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else begin
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if(i3_XmitState==`cXmitCONFIG) r16_CtrlReg0[9] <= 1'b0;
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if(i3_XmitState==`cXmitCONFIG) r16_CtrlReg0[9] <= 1'b0;
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r16_CtrlReg0[15] <= 1'b0;
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r16_CtrlReg0[15] <= 1'b0;
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end
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end
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if(w_WritePulse && w5_Addr==5'b00100) r16_CtrlReg4 <= w16_WrData;
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if(w_WritePulse && w5_Addr==5'b00100) r16_CtrlReg4 <= w16_WrData;
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if(w_WritePulse && w5_Addr==5'b01000) r21_LinkTimer[15:00] <= w16_WrData;
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if(w_WritePulse && w5_Addr==5'b01000) r21_LinkTimer[15:00] <= w16_WrData;
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if(w_WritePulse && w5_Addr==5'b01001) r21_LinkTimer[20:16] <= w16_WrData[4:0];
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if(w_WritePulse && w5_Addr==5'b01001) r21_LinkTimer[20:16] <= w16_WrData[4:0];
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if(w_WritePulse && w5_Addr==5'b01010) r16_ScratchRev <= w16_WrData;
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if(w_WritePulse && w5_Addr==5'b01010) r16_ScratchRev <= w16_WrData;
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if(w_WritePulse && w5_Addr==5'b11111) r16_ModeReg <= w16_WrData;
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if(w_WritePulse && w5_Addr==5'b11111) r16_ModeReg <= w16_WrData;
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//Read Controller
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//Read Controller
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r_Read <= w_Read;
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r_Read <= w_Read;
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if(w_ReadPulse)
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if(w_ReadPulse)
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case(w5_Addr)
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case(w5_Addr)
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5'h00: o32_RdData <= {16'h0,r16_CtrlReg0};
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5'h00: o32_RdData <= {16'h0,r16_CtrlReg0};
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5'h01: o32_RdData <= {16'h0,w16_StatusReg1};
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5'h01: o32_RdData <= {16'h0,w16_StatusReg1};
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5'h02: o32_RdData <= 32'h0;
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5'h02: o32_RdData <= 32'h0;
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5'h03: o32_RdData <= 32'h0;
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5'h03: o32_RdData <= 32'h0;
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5'h04: o32_RdData <= {16'h0,w16_LcAdvAbility};
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5'h04: o32_RdData <= {16'h0,w16_LcAdvAbility};
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5'h05: o32_RdData <= {16'h0,i16_LpAdvAbility};
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5'h05: o32_RdData <= {16'h0,i16_LpAdvAbility};
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5'h08: o32_RdData <= {16'h0,r21_LinkTimer[15:00]};
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5'h08: o32_RdData <= {16'h0,r21_LinkTimer[15:00]};
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5'h09: o32_RdData <= {16'h0,11'h0,r21_LinkTimer[20:16]};
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5'h09: o32_RdData <= {16'h0,11'h0,r21_LinkTimer[20:16]};
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5'h0A: o32_RdData <= r16_ScratchRev;
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5'h0A: o32_RdData <= r16_ScratchRev;
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5'h1F: o32_RdData <= r16_ModeReg;
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5'h1F: o32_RdData <= r16_ModeReg;
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default: o32_RdData <= 32'h0;
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default: o32_RdData <= 32'h0;
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endcase
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endcase
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end
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end
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assign o_ANRestart = r16_CtrlReg0[9];
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assign o_ANRestart = r16_CtrlReg0[9];
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assign o_MIIRst_L = ~r16_CtrlReg0[15];
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assign o_MIIRst_L = ~r16_CtrlReg0[15];
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assign o_ANEnable = r16_CtrlReg0[12];
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assign o_ANEnable = r16_CtrlReg0[12];
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assign o_Loopback = r16_CtrlReg0[14];
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assign o_Loopback = r16_CtrlReg0[14];
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assign o_GxBPowerDown = r16_CtrlReg0[11];
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assign o_GxBPowerDown = r16_CtrlReg0[11];
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assign o16_LcAdvAbility = w16_LcAdvAbility;
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assign o16_LcAdvAbility = w16_LcAdvAbility;
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assign w16_LcAdvAbility = (w_UseAsSGMII==1'b0)?({1'b0,i16_TxConfigReg[15],r16_CtrlReg4[13:12],3'b000,r16_CtrlReg4[8:7],2'b01,5'b00000})://1000-X mode
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assign w16_LcAdvAbility = (w_UseAsSGMII==1'b0)?({1'b0,i16_TxConfigReg[15],r16_CtrlReg4[13:12],3'b000,r16_CtrlReg4[8:7],2'b01,5'b00000})://1000-X mode
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((w_SGMII_PHY==1'b1)?({i_PhyLink,i16_TxConfigReg[15],1'b0,i_PhyDuplex,i2_PhySpeed,10'h1}):
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((w_SGMII_PHY==1'b1)?({i_PhyLink,i16_TxConfigReg[15],1'b0,(i_PhyDuplex|r16_CtrlReg4[12]),(i2_PhySpeed|r16_CtrlReg4[11:10]),10'h1})://SGMII mode - PHY Side
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({1'b0,i16_TxConfigReg[15],1'b0,3'b000,10'h1}));//SGMII mode - MAC Side
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({1'b0,i16_TxConfigReg[15],1'b0,3'b000,10'h1}));//SGMII mode - MAC Side
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assign w16_StatusReg1 = {9'h0,i_ANComplete,2'b01,i_SyncStatus,2'b0};
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assign w16_StatusReg1 = {9'h0,i_ANComplete,2'b01,i_SyncStatus,2'b0};
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assign w_UseAsSGMII = r16_ModeReg[0];
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assign w_UseAsSGMII = r16_ModeReg[0];
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assign w_SGMII_PHY = r16_ModeReg[1];
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assign w_SGMII_PHY = r16_ModeReg[1];
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assign w_UseLcConfig = r16_ModeReg[2];
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assign w_UseLcConfig = r16_ModeReg[2];
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assign o2_SGMIISpeed = (w_UseAsSGMII==1'b0)?2'b10:((w_UseLcConfig==1'b0)?i16_LpAdvAbility[11:10]:{r16_CtrlReg0[6],r16_CtrlReg0[13]});
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assign o2_SGMIISpeed = (w_UseAsSGMII==1'b0)?2'b10:((w_UseLcConfig==1'b0)?i16_LpAdvAbility[11:10]:{r16_CtrlReg0[6],r16_CtrlReg0[13]});
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assign o_SGMIIDuplex = (w_UseAsSGMII==1'b0)?1'b1:((w_UseLcConfig==1'b0)?i16_LpAdvAbility[12]:{r16_CtrlReg0[8]});
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assign o_SGMIIDuplex = (w_UseAsSGMII==1'b0)?1'b1:((w_UseLcConfig==1'b0)?i16_LpAdvAbility[12]:{r16_CtrlReg0[8]});
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endmodule
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endmodule
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