/*
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/*
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Developed By Subtleware Corporation Pte Ltd 2011
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Developed By Subtleware Corporation Pte Ltd 2011
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File :
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File :
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Description :
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Description :
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Remarks :
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Remarks :
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Revision :
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Revision :
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Date Author Description
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Date Author Description
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02/09/12 Jefflieu
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02/09/12 Jefflieu
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*/
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*/
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`include "SGMIIDefs.v"
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`include "SGMIIDefs.v"
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module mTransmit(
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module mTransmit(
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input [02:00] i3_Xmit,
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input [02:00] i3_Xmit,
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input [15:00] i16_ConfigReg,
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input [15:00] i16_ConfigReg,
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input i_TxEN,
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input i_TxEN,
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input i_TxER,
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input i_TxER,
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input [07:00] i8_TxD,
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input [07:00] i8_TxD,
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output reg o_Xmitting,
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output reg o_Xmitting,
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output reg o_TxEven,
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output reg o_TxEven,
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output reg [07:00] o8_TxCodeGroupOut,
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output reg [07:00] o8_TxCodeGroupOut,
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output o_TxCodeValid,
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output o_TxCodeValid,
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output reg o_TxCodeCtrl,
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output reg o_TxCodeCtrl,
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input i_CurrentParity,
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input i_CurrentParity,
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input i_Clk,
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input i_Clk,
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input i_ARst_L);
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input i_ARst_L);
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/*
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/*
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- Transmit order set Statemachine : OSState
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- Transmit order set Statemachine : OSState
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*/
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*/
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localparam stTX_TEST = 24'h000001; //Initial State
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localparam stTX_TEST = 24'h000001; //Initial State
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localparam stCONFIG_C1A= 24'h000002; //Configuration phase
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localparam stCONFIG_C1A= 24'h000002; //Configuration phase
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localparam stCONFIG_C1B= 24'h000004; //Configuration phase
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localparam stCONFIG_C1B= 24'h000004; //Configuration phase
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localparam stCONFIG_C1C= 24'h000008; //Configuration phase
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localparam stCONFIG_C1C= 24'h000008; //Configuration phase
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localparam stCONFIG_C1D= 24'h000010; //Configuration phase
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localparam stCONFIG_C1D= 24'h000010; //Configuration phase
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localparam stCONFIG_C2A= 24'h000020; //Configuration phase
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localparam stCONFIG_C2A= 24'h000020; //Configuration phase
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localparam stCONFIG_C2B= 24'h000040; //Configuration phase
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localparam stCONFIG_C2B= 24'h000040; //Configuration phase
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localparam stCONFIG_C2C= 24'h000080; //Configuration phase
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localparam stCONFIG_C2C= 24'h000080; //Configuration phase
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localparam stCONFIG_C2D= 24'h000100; //Configuration phase
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localparam stCONFIG_C2D= 24'h000100; //Configuration phase
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localparam stTX_IDLE = 24'h000200; //IDLE Phase, Trasmitting Comma Character, this is to wait to sync with the MAC's packet
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localparam stTX_IDLE = 24'h000200; //IDLE Phase, Trasmitting Comma Character, this is to wait to sync with the MAC's packet
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localparam stXMIT_DATA = 24'h000400; //Data Phase, Trasmitting Comma Character
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localparam stXMIT_DATA = 24'h000400; //Data Phase, Trasmitting Comma Character
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localparam stIDLE_DATA = 24'h000800; //Trasmitting Data Character of /I/ Ordered Set
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localparam stIDLE_DATA = 24'h000800; //Trasmitting Data Character of /I/ Ordered Set
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localparam stTX_SOP = 24'h001000; //Transmitting SOP
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localparam stTX_SOP = 24'h001000; //Transmitting SOP
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localparam stTX_PKT = 24'h002000; //False state
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localparam stTX_PKT = 24'h002000; //False state
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localparam stTX_DATA = 24'h004000; //Transmitting Data
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localparam stTX_DATA = 24'h004000; //Transmitting Data
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localparam stTX_EOP = 24'h008000; //End of packet without any extension, tramitting T
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localparam stTX_EOP = 24'h008000; //End of packet without any extension, tramitting T
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localparam stTX_EOP_EXT= 24'h010000; //End of packet with extension
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localparam stTX_EOP_EXT= 24'h010000; //End of packet with extension
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localparam stTX_EXT_1 = 24'h020000; //Extend 1 cycle to align the COMMA to Even Code group
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localparam stTX_EXT_1 = 24'h020000; //Extend 1 cycle to align the COMMA to Even Code group
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localparam stEPD2_NOEXT= 24'h040000; //Second Cycle of EPD, transmitting /R/
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localparam stEPD2_NOEXT= 24'h040000; //Second Cycle of EPD, transmitting /R/
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localparam stEPD3 = 24'h080000; //Third Cycle of EPD, transmitting /R/
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localparam stEPD3 = 24'h080000; //Third Cycle of EPD, transmitting /R/
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localparam stCARR_EXT = 24'h100000; //Carrier extension
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localparam stCARR_EXT = 24'h100000; //Carrier extension
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localparam stALIGN_ERR = 24'h200000; //Repeater's state, we don't use this, go straight to START ERR
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//localparam stALIGN_ERR = 24'h200000; //Repeater's state, we don't use this, go straight to START ERR
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localparam stSTART_ERR = 24'h400000; //Repeater's state
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localparam stSTART_ERR = 24'h200000; //Repeater's state
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localparam stTX_ERR = 24'h800000; //Repeater's state
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localparam stTX_ERR = 24'h400000; //Repeater's state
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reg [23:00] r24_State;
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reg [22:00] r13_State;
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reg [23:00] w24_NxtState;
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reg [22:00] w24_NxtState;
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wire w_XmitChange;
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wire w_XmitChange;
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reg [02:00] r3_LstXmit;
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reg [02:00] r3_LstXmit;
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reg r_TxEven;
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reg r_TxEven;
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wire w_TxOSIndicate;
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wire w_TxOSIndicate;
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wire w_FifoTxEn;
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wire w_FifoTxEn;
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wire w_FifoTxEr;
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wire w_FifoTxEr;
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wire [07:00] w8_FifoData;
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wire [07:00] w8_FifoData;
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wire w_UpdateXmitChange;
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wire w_UpdateXmitChange;
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wire w_ResetState;
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wire w_ResetState;
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wire r_ToTxData; //This signal used in txIDLE_DATA state to comeback to TXIDLE or TXDATA
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reg r_ToTxData; //This signal used in txIDLE_DATA state to comeback to TXIDLE or TXDATA
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wire w_Disparity;
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wire w_Disparity;
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wire [09:00] w10_FifoDin;
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wire [09:00] w10_FifoDin;
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wire [09:00] w10_FifoQ;
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wire [09:00] w10_FifoQ;
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wire w_FifoRd,w_FifoEmpty;
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wire w_FifoRd,w_FifoEmpty;
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reg [07:00] r8_TxData;
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reg [07:00] r8_TxData;
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assign w_XmitChange = (r3_LstXmit!=i3_Xmit)?1'b1:1'b0;
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assign w_XmitChange = (r3_LstXmit!=i3_Xmit)?1'b1:1'b0;
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assign w_TxOSIndicate = (r24_State==stCONFIG_C1A||r24_State==stCONFIG_C1B||r24_State==stCONFIG_C1C||
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assign w_TxOSIndicate = (r13_State==stCONFIG_C1A||r13_State==stCONFIG_C1B||r13_State==stCONFIG_C1C||
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r24_State==stCONFIG_C2A||r24_State==stCONFIG_C2B||r24_State==stCONFIG_C2C||
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r13_State==stCONFIG_C2A||r13_State==stCONFIG_C2B||r13_State==stCONFIG_C2C||
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r24_State==stTX_IDLE||r24_State==stTX_DATA)?1'b0:1'b1;
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r13_State==stTX_IDLE||r13_State==stTX_DATA)?1'b0:1'b1;
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//assign w_UpdateXmitChange =
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//assign w_UpdateXmitChange =
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//FIFO
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//FIFO
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assign w10_FifoDin = {i_TxEN,i_TxER,i8_TxD};
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assign w10_FifoDin = {i_TxEN,i_TxER,i8_TxD};
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assign w_FifoTxEn = w10_FifoQ[9] & (~w_FifoEmpty);
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assign w_FifoTxEn = w10_FifoQ[9] & (~w_FifoEmpty);
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assign w_FifoTxEr = w10_FifoQ[8] & (~w_FifoEmpty);
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assign w_FifoTxEr = w10_FifoQ[8] & (~w_FifoEmpty);
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assign w8_FifoData = w10_FifoQ[7:0];
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assign w8_FifoData = w10_FifoQ[7:0];
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mSyncFifo #(.pDataWidth(10),.pPtrWidth(2)) u0SyncFifo (
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mSyncFifo #(.pDataWidth(10),.pPtrWidth(2)) u0SyncFifo (
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.iv_Din(w10_FifoDin),
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.iv_Din(w10_FifoDin),
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.i_Wr((i_TxEN|i_TxER)),
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.i_Wr((i_TxEN|i_TxER)),
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.i_Rd(w_FifoRd),
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.i_Rd(w_FifoRd),
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.o_Empty(w_FifoEmpty),
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.o_Empty(w_FifoEmpty),
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.o_Full(),
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.o_Full(),
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.ov_Q(w10_FifoQ),
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.ov_Q(w10_FifoQ),
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.i_Clk(i_Clk),
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.i_Clk(i_Clk),
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.i_ARst_L(i_ARst_L));
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.i_ARst_L(i_ARst_L));
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//END FIFO
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//END FIFO
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assign w_FifoRd = ((w_FifoTxEn && (r24_State==stXMIT_DATA||r24_State==stTX_IDLE)))?1'b0:1'b1;
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assign w_FifoRd = ((w_FifoTxEn && (r13_State==stXMIT_DATA||r13_State==stTX_IDLE)))?1'b0:1'b1;
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always@(posedge i_Clk or negedge i_ARst_L)
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always@(posedge i_Clk or negedge i_ARst_L)
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if(i_ARst_L==1'b0) begin
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if(i_ARst_L==1'b0) begin
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r24_State <= stTX_TEST;
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r13_State <= stTX_TEST;
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r3_LstXmit <= 3'b000;
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r3_LstXmit <= `cXmitIDLE;
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r_TxEven <= 1'b0;
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r_TxEven <= 1'b0;
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o_TxEven <= 1'b1;
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end
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end
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else
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else
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begin
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begin
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if(w_UpdateXmitChange) r3_LstXmit <= i3_Xmit;
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if(w_UpdateXmitChange) r3_LstXmit <= i3_Xmit;
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r24_State <= w24_NxtState;
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if(w_ResetState)
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r13_State <= stTX_TEST;
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else
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r13_State <= w24_NxtState;
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r_TxEven <= ~r_TxEven;
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r_TxEven <= ~r_TxEven;
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o_TxEven <= r_TxEven;
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o_TxEven <= r_TxEven;
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end
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end
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// always@(posedge i_Clk or posedge w_ResetState)
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// if(w_ResetState)
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// r13_State <= stTX_TEST;
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// else
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// r13_State <= w24_NxtState;
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assign w_UpdateXmitChange = w_ResetState;
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assign w_UpdateXmitChange = w_ResetState;
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assign w_ResetState = (i_ARst_L==1'b0)||(w_XmitChange && (r_TxEven==1'b0) && w_TxOSIndicate);
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assign w_ResetState = (i_ARst_L==1'b0)||(w_XmitChange && (o_TxEven==1'b0) && w_TxOSIndicate);
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assign w_Disparity = i_CurrentParity;
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assign w_Disparity = i_CurrentParity;
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always@(*)
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always@(*)
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begin
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begin
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if(w_ResetState)
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r24_State <= stTX_TEST;
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// else
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case(r24_State)
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case(r13_State)
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stTX_TEST : if(i3_Xmit==`cXmitCONFIG && r_TxEven==1'b0) w24_NxtState <= stCONFIG_C1A; else
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stTX_TEST : if(i3_Xmit==`cXmitCONFIG && o_TxEven==1'b0) w24_NxtState <= stCONFIG_C1A; else
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if(i3_Xmit==`cXmitIDLE || (i3_Xmit==`cXmitDATA && (w_FifoTxEn || w_FifoTxEr))) w24_NxtState <= stTX_IDLE; else
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if((i3_Xmit==`cXmitIDLE &&(~o_TxEven)) || ((~o_TxEven) && i3_Xmit==`cXmitDATA && (w_FifoTxEn || w_FifoTxEr))) w24_NxtState <= stTX_IDLE; else
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if(i3_Xmit==`cXmitDATA && (~w_FifoTxEn) && (~w_FifoTxEr)) w24_NxtState <= stXMIT_DATA;
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if(i3_Xmit==`cXmitDATA && (~w_FifoTxEn) && (~w_FifoTxEr)) w24_NxtState <= stXMIT_DATA;
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else w24_NxtState <= stTX_TEST;
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else w24_NxtState <= stTX_TEST;
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stCONFIG_C1A : w24_NxtState <= stCONFIG_C1B;
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stCONFIG_C1A : w24_NxtState <= stCONFIG_C1B;
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stCONFIG_C1B : w24_NxtState <= stCONFIG_C1C;
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stCONFIG_C1B : w24_NxtState <= stCONFIG_C1C;
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stCONFIG_C1C : w24_NxtState <= stCONFIG_C1D;
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stCONFIG_C1C : w24_NxtState <= stCONFIG_C1D;
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stCONFIG_C1D : if(i3_Xmit==`cXmitCONFIG) w24_NxtState <= stCONFIG_C2A; else
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stCONFIG_C1D : if(i3_Xmit==`cXmitCONFIG) w24_NxtState <= stCONFIG_C2A; else
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if(i3_Xmit==`cXmitIDLE || (i3_Xmit==`cXmitDATA && (w_FifoTxEn || w_FifoTxEr))) w24_NxtState <= stTX_IDLE; else
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if(i3_Xmit==`cXmitIDLE || (i3_Xmit==`cXmitDATA && (w_FifoTxEn || w_FifoTxEr))) w24_NxtState <= stTX_IDLE; else
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if(i3_Xmit==`cXmitDATA && (~w_FifoTxEn) && (~w_FifoTxEr)) w24_NxtState <= stXMIT_DATA; else
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if(i3_Xmit==`cXmitDATA && (~w_FifoTxEn) && (~w_FifoTxEr)) w24_NxtState <= stXMIT_DATA; else
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w24_NxtState <= stTX_ERR;
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w24_NxtState <= stTX_ERR;
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stCONFIG_C2A : w24_NxtState <= stCONFIG_C2B;
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stCONFIG_C2A : w24_NxtState <= stCONFIG_C2B;
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stCONFIG_C2B : w24_NxtState <= stCONFIG_C2C;
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stCONFIG_C2B : w24_NxtState <= stCONFIG_C2C;
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stCONFIG_C2C : w24_NxtState <= stCONFIG_C2D;
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stCONFIG_C2C : w24_NxtState <= stCONFIG_C2D;
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stCONFIG_C2D : if(i3_Xmit==`cXmitCONFIG) w24_NxtState <= stCONFIG_C1A; else
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stCONFIG_C2D : if(i3_Xmit==`cXmitCONFIG) w24_NxtState <= stCONFIG_C1A; else
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if(i3_Xmit==`cXmitIDLE || (i3_Xmit==`cXmitDATA && (w_FifoTxEn || w_FifoTxEr))) w24_NxtState <= stTX_IDLE; else
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if(i3_Xmit==`cXmitIDLE || (i3_Xmit==`cXmitDATA && (w_FifoTxEn || w_FifoTxEr))) w24_NxtState <= stTX_IDLE; else
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if(i3_Xmit==`cXmitDATA && (~w_FifoTxEn) && (~w_FifoTxEr)) w24_NxtState <= stXMIT_DATA; else
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if(i3_Xmit==`cXmitDATA && (~w_FifoTxEn) && (~w_FifoTxEr)) w24_NxtState <= stXMIT_DATA; else
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w24_NxtState <= stTX_ERR;
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w24_NxtState <= stTX_ERR;
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stTX_IDLE : w24_NxtState <= stIDLE_DATA;
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stTX_IDLE : w24_NxtState <= stIDLE_DATA;
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stIDLE_DATA : if(r_ToTxData==1'b0) begin //Data phase of TX_IDLE
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stIDLE_DATA : if(r_ToTxData==1'b0) begin //Data phase of TX_IDLE
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if(i3_Xmit==`cXmitDATA && (~w_FifoTxEn) && (~w_FifoTxEr)) w24_NxtState <= stXMIT_DATA; else
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if(i3_Xmit==`cXmitDATA && (~w_FifoTxEn) && (~w_FifoTxEr)) w24_NxtState <= stXMIT_DATA; else
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w24_NxtState <= stTX_IDLE;
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w24_NxtState <= stTX_IDLE;
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end
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end
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else
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else
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begin
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begin
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if(w_FifoTxEn & (~w_FifoTxEr)) w24_NxtState <= stTX_SOP; else
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if(w_FifoTxEn & (~w_FifoTxEr)) w24_NxtState <= stTX_SOP; else
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if(w_FifoTxEn & w_FifoTxEr) w24_NxtState <= stSTART_ERR; else
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if(w_FifoTxEn & w_FifoTxEr) w24_NxtState <= stSTART_ERR; else
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w24_NxtState <= stXMIT_DATA;
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w24_NxtState <= stXMIT_DATA;
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end
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end
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stXMIT_DATA : w24_NxtState <= stIDLE_DATA;
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stXMIT_DATA : w24_NxtState <= stIDLE_DATA;
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stTX_DATA : if(w_FifoTxEn) w24_NxtState <= stTX_DATA; else
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stTX_DATA : if(w_FifoTxEn) w24_NxtState <= stTX_DATA; else
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if((~w_FifoTxEn) & (~w_FifoTxEr)) w24_NxtState <= stTX_EOP; else
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if((~w_FifoTxEn) & (~w_FifoTxEr)) w24_NxtState <= stTX_EOP; else
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w24_NxtState <= stTX_EOP_EXT;
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w24_NxtState <= stTX_EOP_EXT;
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stTX_SOP : if(w_FifoTxEn) w24_NxtState <= stTX_DATA; else
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stTX_SOP : if(w_FifoTxEn) w24_NxtState <= stTX_DATA; else
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if((~w_FifoTxEn) & (~w_FifoTxEr)) w24_NxtState <= stTX_EOP; else
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if((~w_FifoTxEn) & (~w_FifoTxEr)) w24_NxtState <= stTX_EOP; else
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w24_NxtState <= stTX_EOP_EXT;
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w24_NxtState <= stTX_EOP_EXT;
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stTX_EOP : w24_NxtState <= stEPD2_NOEXT;
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stTX_EOP : w24_NxtState <= stEPD2_NOEXT;
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stEPD2_NOEXT : if(r_TxEven) w24_NxtState <= stEPD3; else
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stEPD2_NOEXT : if(r_TxEven) w24_NxtState <= stEPD3; else
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w24_NxtState <= stXMIT_DATA;
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w24_NxtState <= stXMIT_DATA;
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stEPD3 : w24_NxtState <= stXMIT_DATA;
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stEPD3 : w24_NxtState <= stXMIT_DATA;
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stTX_EOP_EXT : if(~w_FifoTxEr) w24_NxtState <= stTX_EXT_1; else w24_NxtState <= stCARR_EXT;
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stTX_EOP_EXT : if(~w_FifoTxEr) w24_NxtState <= stTX_EXT_1; else w24_NxtState <= stCARR_EXT;
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stTX_EXT_1 : w24_NxtState <= stEPD2_NOEXT;
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stTX_EXT_1 : w24_NxtState <= stEPD2_NOEXT;
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stCARR_EXT : if((~w_FifoTxEn) & (~w_FifoTxEr)) w24_NxtState <= stTX_EXT_1; else
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stCARR_EXT : if((~w_FifoTxEn) & (~w_FifoTxEr)) w24_NxtState <= stTX_EXT_1; else
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if(w_FifoTxEn & (~w_FifoTxEr)) w24_NxtState <= stTX_SOP; else
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if(w_FifoTxEn & (~w_FifoTxEr)) w24_NxtState <= stTX_SOP; else
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if(w_FifoTxEn & w_FifoTxEr) w24_NxtState <= stSTART_ERR; else
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if(w_FifoTxEn & w_FifoTxEr) w24_NxtState <= stSTART_ERR; else
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w24_NxtState <= stCARR_EXT;
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w24_NxtState <= stCARR_EXT;
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//stALIGN_ERR :
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//stALIGN_ERR :
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stSTART_ERR : w24_NxtState <= stTX_ERR;
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stSTART_ERR : w24_NxtState <= stTX_ERR;
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stTX_ERR : if(w_FifoTxEn) w24_NxtState <= stTX_DATA; else
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stTX_ERR : if(w_FifoTxEn) w24_NxtState <= stTX_DATA; else
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if((~w_FifoTxEn) & (~w_FifoTxEr)) w24_NxtState <= stTX_EOP; else
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if((~w_FifoTxEn) & (~w_FifoTxEr)) w24_NxtState <= stTX_EOP; else
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w24_NxtState <= stTX_EOP_EXT;
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w24_NxtState <= stTX_EOP_EXT;
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endcase
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endcase
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end
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end
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assign o_TxCodeValid = 1'b1;
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assign o_TxCodeValid = 1'b1;
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always@(posedge i_Clk or negedge i_ARst_L)
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always@(posedge i_Clk or negedge i_ARst_L)
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if(i_ARst_L==1'b0) begin
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if(i_ARst_L==1'b0) begin
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o_Xmitting <= 1'b0;
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o_Xmitting <= 1'b0;
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o_TxCodeCtrl <= 1'b0;
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o_TxCodeCtrl <= 1'b0;
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o8_TxCodeGroupOut <= 8'h00;
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o8_TxCodeGroupOut <= 8'h00;
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end else begin
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end else begin
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case(w24_NxtState)
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case(w24_NxtState)
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stTX_TEST : begin
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stTX_TEST : begin
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o_Xmitting <= 1'b0;
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o_Xmitting <= 1'b0;
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end
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end
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stCONFIG_C1A : begin
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stCONFIG_C1A : begin
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o8_TxCodeGroupOut <= `K28_5;
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o8_TxCodeGroupOut <= `K28_5;
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o_TxCodeCtrl <= 1'b1;
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o_TxCodeCtrl <= 1'b1;
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end
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end
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stCONFIG_C1B : begin
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stCONFIG_C1B : begin
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o8_TxCodeGroupOut <= `D21_5;
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o8_TxCodeGroupOut <= `D21_5;
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o_TxCodeCtrl <= 1'b0;
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o_TxCodeCtrl <= 1'b0;
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end
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end
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stCONFIG_C1C : o8_TxCodeGroupOut <= i16_ConfigReg[07:00];
|
stCONFIG_C1C : o8_TxCodeGroupOut <= i16_ConfigReg[07:00];
|
stCONFIG_C1D : o8_TxCodeGroupOut <= i16_ConfigReg[15:08];
|
stCONFIG_C1D : o8_TxCodeGroupOut <= i16_ConfigReg[15:08];
|
|
|
stCONFIG_C2A : begin
|
stCONFIG_C2A : begin
|
o8_TxCodeGroupOut <= `K28_5;
|
o8_TxCodeGroupOut <= `K28_5;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
end
|
end
|
stCONFIG_C2B : begin
|
stCONFIG_C2B : begin
|
o8_TxCodeGroupOut <= `D2_2;
|
o8_TxCodeGroupOut <= `D2_2;
|
o_TxCodeCtrl <= 1'b0;
|
o_TxCodeCtrl <= 1'b0;
|
end
|
end
|
stCONFIG_C2C : o8_TxCodeGroupOut <= i16_ConfigReg[07:00];
|
stCONFIG_C2C : o8_TxCodeGroupOut <= i16_ConfigReg[07:00];
|
stCONFIG_C2D : o8_TxCodeGroupOut <= i16_ConfigReg[15:08];
|
stCONFIG_C2D : o8_TxCodeGroupOut <= i16_ConfigReg[15:08];
|
stTX_IDLE : begin
|
stTX_IDLE : begin
|
o8_TxCodeGroupOut <= `K28_5;
|
o8_TxCodeGroupOut <= `K28_5;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
|
r_ToTxData <= 1'b0;
|
end
|
end
|
stIDLE_DATA : begin
|
stIDLE_DATA : begin
|
o8_TxCodeGroupOut <= (w_Disparity==1'b0)?`D5_6:`D16_2;//Disparity = 0 means positive
|
o8_TxCodeGroupOut <= (w_Disparity==1'b1)?`D5_6:`D16_2;//Disparity = 1 means positive
|
o_TxCodeCtrl <= 1'b0;
|
o_TxCodeCtrl <= 1'b0;
|
end
|
end
|
stXMIT_DATA : begin
|
stXMIT_DATA : begin
|
o8_TxCodeGroupOut <= `K28_5;
|
o8_TxCodeGroupOut <= `K28_5;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
|
r_ToTxData <= 1'b1;
|
end
|
end
|
stTX_DATA : if(((~w_FifoTxEn) & w_FifoTxEr & w8_FifoData != 8'h0F)||(w_FifoTxEn & w_FifoTxEr))
|
stTX_DATA : if(((~w_FifoTxEn) & w_FifoTxEr & w8_FifoData != 8'h0F)||(w_FifoTxEn & w_FifoTxEr))
|
begin
|
begin
|
o8_TxCodeGroupOut <= `K30_7;
|
o8_TxCodeGroupOut <= `K30_7;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
end else
|
end else
|
begin
|
begin
|
o8_TxCodeGroupOut <= w8_FifoData;
|
o8_TxCodeGroupOut <= w8_FifoData;
|
o_TxCodeCtrl <= 1'b0;
|
o_TxCodeCtrl <= 1'b0;
|
end
|
end
|
stTX_SOP : begin
|
stTX_SOP : begin
|
o_Xmitting <= 1'b1;
|
o_Xmitting <= 1'b1;
|
o8_TxCodeGroupOut <= `K27_7;
|
o8_TxCodeGroupOut <= `K27_7;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
end
|
end
|
stTX_EOP : begin
|
stTX_EOP : begin
|
o8_TxCodeGroupOut <= `K29_7;
|
o8_TxCodeGroupOut <= `K29_7;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
o_Xmitting <= (~r_TxEven);
|
o_Xmitting <= (~r_TxEven);
|
end
|
end
|
stEPD2_NOEXT : begin
|
stEPD2_NOEXT : begin
|
o8_TxCodeGroupOut <= `K23_7;
|
o8_TxCodeGroupOut <= `K23_7;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
o_Xmitting <= 1'b0;
|
o_Xmitting <= 1'b0;
|
end
|
end
|
stEPD3 : begin
|
stEPD3 : begin
|
o8_TxCodeGroupOut <= `K23_7;
|
o8_TxCodeGroupOut <= `K23_7;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
end
|
end
|
stTX_EOP_EXT : if(((~w_FifoTxEn) & w_FifoTxEr & w8_FifoData != 8'h0F)||(w_FifoTxEn & w_FifoTxEr))
|
stTX_EOP_EXT : if(((~w_FifoTxEn) & w_FifoTxEr & w8_FifoData != 8'h0F)||(w_FifoTxEn & w_FifoTxEr))
|
begin
|
begin
|
o8_TxCodeGroupOut <= `K30_7;
|
o8_TxCodeGroupOut <= `K30_7;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
end else
|
end else
|
begin
|
begin
|
o8_TxCodeGroupOut <= `K29_7;
|
o8_TxCodeGroupOut <= `K29_7;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
end
|
end
|
stTX_EXT_1 : begin
|
stTX_EXT_1 : begin
|
o_Xmitting <= (~r_TxEven);
|
o_Xmitting <= (~r_TxEven);
|
if(((~w_FifoTxEn) & w_FifoTxEr & w8_FifoData != 8'h0F)||(w_FifoTxEn & w_FifoTxEr))
|
if(((~w_FifoTxEn) & w_FifoTxEr & w8_FifoData != 8'h0F)||(w_FifoTxEn & w_FifoTxEr))
|
begin
|
begin
|
o8_TxCodeGroupOut <= `K30_7;
|
o8_TxCodeGroupOut <= `K30_7;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
|
|
end else
|
end else
|
begin
|
begin
|
o8_TxCodeGroupOut <= `K23_7;
|
o8_TxCodeGroupOut <= `K23_7;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
end
|
end
|
end
|
end
|
stCARR_EXT : if(((~w_FifoTxEn) & w_FifoTxEr & w8_FifoData != 8'h0F)||(w_FifoTxEn & w_FifoTxEr))
|
stCARR_EXT : if(((~w_FifoTxEn) & w_FifoTxEr & w8_FifoData != 8'h0F)||(w_FifoTxEn & w_FifoTxEr))
|
begin
|
begin
|
o8_TxCodeGroupOut <= `K30_7;
|
o8_TxCodeGroupOut <= `K30_7;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
end else
|
end else
|
begin
|
begin
|
o8_TxCodeGroupOut <= `K23_7;
|
o8_TxCodeGroupOut <= `K23_7;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
end
|
end
|
|
|
//stALIGN_ERR :
|
//stALIGN_ERR :
|
stSTART_ERR : begin
|
stSTART_ERR : begin
|
o8_TxCodeGroupOut <= `K27_7;
|
o8_TxCodeGroupOut <= `K27_7;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
o_Xmitting <= 1'b1;
|
o_Xmitting <= 1'b1;
|
end
|
end
|
stTX_ERR : begin
|
stTX_ERR : begin
|
o8_TxCodeGroupOut <= `K30_7;
|
o8_TxCodeGroupOut <= `K30_7;
|
o_TxCodeCtrl <= 1'b1;
|
o_TxCodeCtrl <= 1'b1;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//synthesis translate_off
|
//synthesis translate_off
|
reg [239:0] r240_TxStateName;
|
reg [239:0] r240_TxStateName;
|
always@(*)
|
always@(*)
|
case(r24_State)
|
case(r13_State)
|
stTX_TEST : r240_TxStateName<="stTX_TEST ";
|
stTX_TEST : r240_TxStateName<="stTX_TEST ";
|
stCONFIG_C1A : r240_TxStateName<="stCONFIG_C1A";
|
stCONFIG_C1A : r240_TxStateName<="stCONFIG_C1A";
|
stCONFIG_C1B : r240_TxStateName<="stCONFIG_C1B";
|
stCONFIG_C1B : r240_TxStateName<="stCONFIG_C1B";
|
stCONFIG_C1C : r240_TxStateName<="stCONFIG_C1C";
|
stCONFIG_C1C : r240_TxStateName<="stCONFIG_C1C";
|
stCONFIG_C1D : r240_TxStateName<="stCONFIG_C1D";
|
stCONFIG_C1D : r240_TxStateName<="stCONFIG_C1D";
|
stCONFIG_C2A : r240_TxStateName<="stCONFIG_C2A";
|
stCONFIG_C2A : r240_TxStateName<="stCONFIG_C2A";
|
stCONFIG_C2B : r240_TxStateName<="stCONFIG_C2B";
|
stCONFIG_C2B : r240_TxStateName<="stCONFIG_C2B";
|
stCONFIG_C2C : r240_TxStateName<="stCONFIG_C2C";
|
stCONFIG_C2C : r240_TxStateName<="stCONFIG_C2C";
|
stCONFIG_C2D : r240_TxStateName<="stCONFIG_C2D";
|
stCONFIG_C2D : r240_TxStateName<="stCONFIG_C2D";
|
stTX_IDLE : r240_TxStateName<="stTX_IDLE ";
|
stTX_IDLE : r240_TxStateName<="stTX_IDLE ";
|
stXMIT_DATA : r240_TxStateName<="stXMIT_DATA";
|
stXMIT_DATA : r240_TxStateName<="stXMIT_DATA";
|
stIDLE_DATA : r240_TxStateName<="stIDLE_DATA";
|
stIDLE_DATA : r240_TxStateName<="stIDLE_DATA";
|
stTX_SOP : r240_TxStateName<="stTX_SOP ";
|
stTX_SOP : r240_TxStateName<="stTX_SOP ";
|
stTX_PKT : r240_TxStateName<="stTX_PKT ";
|
stTX_PKT : r240_TxStateName<="stTX_PKT ";
|
stTX_DATA : r240_TxStateName<="stTX_DATA ";
|
stTX_DATA : r240_TxStateName<="stTX_DATA ";
|
stTX_EOP : r240_TxStateName<="stTX_EOP ";
|
stTX_EOP : r240_TxStateName<="stTX_EOP ";
|
stTX_EOP_EXT : r240_TxStateName<="stTX_EOP_EXT";
|
stTX_EOP_EXT : r240_TxStateName<="stTX_EOP_EXT";
|
stTX_EXT_1 : r240_TxStateName<="stTX_EXT_1 ";
|
stTX_EXT_1 : r240_TxStateName<="stTX_EXT_1 ";
|
stEPD2_NOEXT : r240_TxStateName<="stEPD2_NOEXT";
|
stEPD2_NOEXT : r240_TxStateName<="stEPD2_NOEXT";
|
stEPD3 : r240_TxStateName<="stEPD3 ";
|
stEPD3 : r240_TxStateName<="stEPD3 ";
|
stCARR_EXT : r240_TxStateName<="stCARR_EXT ";
|
stCARR_EXT : r240_TxStateName<="stCARR_EXT ";
|
stALIGN_ERR : r240_TxStateName<="stALIGN_ERR";
|
//stALIGN_ERR : r240_TxStateName<="stALIGN_ERR";
|
stSTART_ERR : r240_TxStateName<="stSTART_ERR";
|
stSTART_ERR : r240_TxStateName<="stSTART_ERR";
|
stTX_ERR : r240_TxStateName<="stTX_ERR ";
|
stTX_ERR : r240_TxStateName<="stTX_ERR ";
|
endcase
|
endcase
|
//synthesis translate_on
|
//synthesis translate_on
|
endmodule
|
endmodule
|
|
|
