--
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--
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--
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-- This file is a part of JOP, the Java Optimized Processor
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--
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-- Copyright (C) 2001-2008, Martin Schoeberl (martin@jopdesign.com)
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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-- sc_mac.vhd
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-- sc_mac.vhd
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--
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--
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-- A simple MAC unit with a SimpCon interface
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-- A simple MAC unit with a SimpCon interface
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--
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--
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-- Author: Martin Schoeberl martin@jopdesign.com
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-- Author: Martin Schoeberl martin@jopdesign.com
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--
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--
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--
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--
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-- resources on Cyclone
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-- resources on Cyclone
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--
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--
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-- xx LCs, max xx MHz
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-- xx LCs, max xx MHz
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--
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--
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--
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--
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-- 2006-02-12 first version
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-- 2006-02-12 first version
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--
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--
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-- todo:
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-- todo:
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--
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--
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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LIBRARY lpm;
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LIBRARY lpm;
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USE lpm.lpm_components.all;
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USE lpm.lpm_components.all;
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entity mac is
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entity mac is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- SimpCon interface
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-- SimpCon interface
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opa, opb : in std_logic_vector(31 downto 0);
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opa, opb : in std_logic_vector(31 downto 0);
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start : in std_logic;
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start : in std_logic;
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clear : in std_logic;
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clear : in std_logic;
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result : out std_logic_vector(63 downto 0)
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result : out std_logic_vector(63 downto 0)
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);
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);
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end mac;
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end mac;
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architecture rtl of mac is
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architecture rtl of mac is
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (63 DOWNTO 0);
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (63 DOWNTO 0);
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COMPONENT lpm_mult
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COMPONENT lpm_mult
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GENERIC (
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GENERIC (
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lpm_hint : STRING;
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lpm_hint : STRING;
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lpm_pipeline : NATURAL;
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lpm_pipeline : NATURAL;
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lpm_representation : STRING;
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lpm_representation : STRING;
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lpm_type : STRING;
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lpm_type : STRING;
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lpm_widtha : NATURAL;
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lpm_widtha : NATURAL;
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lpm_widthb : NATURAL;
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lpm_widthb : NATURAL;
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lpm_widthp : NATURAL;
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lpm_widthp : NATURAL;
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lpm_widths : NATURAL
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lpm_widths : NATURAL
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);
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);
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PORT (
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PORT (
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dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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clock : IN STD_LOGIC ;
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clock : IN STD_LOGIC ;
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result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
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result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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type state_type is (idle, mul, add);
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type state_type is (idle, mul, add);
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signal state : state_type;
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signal state : state_type;
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signal cnt : unsigned(5 downto 0);
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signal cnt : unsigned(5 downto 0);
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signal mul_res : unsigned(63 downto 0);
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signal mul_res : unsigned(63 downto 0);
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signal acc : unsigned(63 downto 0);
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signal acc : unsigned(63 downto 0);
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begin
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begin
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lpm_mult_component : lpm_mult
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lpm_mult_component : lpm_mult
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GENERIC MAP (
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GENERIC MAP (
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lpm_hint => "MAXIMIZE_SPEED=5",
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lpm_hint => "MAXIMIZE_SPEED=5",
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lpm_pipeline => 16,
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lpm_pipeline => 16,
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lpm_representation => "SIGNED",
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lpm_representation => "SIGNED",
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lpm_type => "LPM_MULT",
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lpm_type => "LPM_MULT",
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lpm_widtha => 32,
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lpm_widtha => 32,
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lpm_widthb => 32,
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lpm_widthb => 32,
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lpm_widthp => 64,
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lpm_widthp => 64,
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lpm_widths => 1
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lpm_widths => 1
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)
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)
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PORT MAP (
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PORT MAP (
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dataa => opa,
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dataa => opa,
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datab => opb,
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datab => opb,
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clock => clk,
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clock => clk,
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result => sub_wire0
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result => sub_wire0
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);
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);
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mul_res <= unsigned(sub_wire0);
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mul_res <= unsigned(sub_wire0);
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process(clk, reset)
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process(clk, reset)
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begin
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begin
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if reset='1' then
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if reset='1' then
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acc <= (others => '0');
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acc <= (others => '0');
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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case state is
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case state is
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when idle =>
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when idle =>
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if start='1' then
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if start='1' then
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state <= mul;
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state <= mul;
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cnt <= "010010"; -- for shure
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cnt <= "010010"; -- for shure
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end if;
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end if;
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when mul =>
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when mul =>
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cnt <= cnt-1;
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cnt <= cnt-1;
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if cnt=0 then
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if cnt=0 then
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state <= add;
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state <= add;
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end if;
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end if;
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when add =>
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when add =>
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acc <= acc + mul_res;
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acc <= acc + mul_res;
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state <= idle;
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state <= idle;
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end case;
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end case;
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if clear='1' then
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if clear='1' then
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acc <= (others => '0');
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acc <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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result <= std_logic_vector(acc);
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result <= std_logic_vector(acc);
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end process;
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end process;
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end rtl;
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end rtl;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity sc_mac is
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entity sc_mac is
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generic (addr_bits : integer; scale : integer := 16);
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generic (addr_bits : integer; scale : integer := 16);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- SimpCon interface
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-- SimpCon interface
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address : in std_logic_vector(addr_bits-1 downto 0);
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address : in std_logic_vector(addr_bits-1 downto 0);
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wr_data : in std_logic_vector(31 downto 0);
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wr_data : in std_logic_vector(31 downto 0);
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rd, wr : in std_logic;
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rd, wr : in std_logic;
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rd_data : out std_logic_vector(31 downto 0);
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rd_data : out std_logic_vector(31 downto 0);
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rdy_cnt : out unsigned(1 downto 0)
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rdy_cnt : out unsigned(1 downto 0)
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);
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);
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end sc_mac;
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end sc_mac;
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architecture rtl of sc_mac is
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architecture rtl of sc_mac is
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signal opa, opb : std_logic_vector(31 downto 0);
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signal opa, opb : std_logic_vector(31 downto 0);
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signal result : std_logic_vector(63 downto 0);
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signal result : std_logic_vector(63 downto 0);
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signal start : std_logic;
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signal start : std_logic;
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signal clear : std_logic;
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signal clear : std_logic;
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begin
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begin
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rdy_cnt <= "00"; -- no wait states, we are hopefully fast enough
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rdy_cnt <= "00"; -- no wait states, we are hopefully fast enough
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cm: entity work.mac
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cm: entity work.mac
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port map(
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port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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opa => opa,
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opa => opa,
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opb => opb,
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opb => opb,
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start => start,
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start => start,
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clear => clear,
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clear => clear,
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result => result
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result => result
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);
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);
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--
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--
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-- SimpCon read and write
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-- SimpCon read and write
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--
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--
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process(clk, reset)
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process(clk, reset)
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begin
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begin
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if reset='1' then
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if reset='1' then
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rd_data <= (others => '0');
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rd_data <= (others => '0');
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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start <= '0';
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start <= '0';
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if wr='1' then
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if wr='1' then
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if address(0)='0' then
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if address(0)='0' then
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opa <= wr_data;
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opa <= wr_data;
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else
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else
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opb <= wr_data;
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opb <= wr_data;
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start <= '1';
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start <= '1';
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end if;
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end if;
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end if;
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end if;
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-- get MAC result scaled by 'scale' and clear the accumulator
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-- get MAC result scaled by 'scale' and clear the accumulator
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clear <= '0';
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clear <= '0';
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if rd='1' then
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if rd='1' then
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-- if address(0)='0' then
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-- if address(0)='0' then
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rd_data <= result(31+scale downto scale);
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rd_data <= result(31+scale downto scale);
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clear <= '1';
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clear <= '1';
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-- else
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-- else
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-- rd_data <= result(63 downto 32);
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-- rd_data <= result(63 downto 32);
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-- end if;
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-- end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end rtl;
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end rtl;
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