-- $Id: phase_detector.vhdl,v 1.3 2005-03-04 08:06:20 arif_endro Exp $
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-- $Id: phase_detector.vhdl,v 1.3 2005-03-04 08:06:20 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Phase detector
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-- Title : Phase detector
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-- Project : FM Receiver
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-- Project : FM Receiver
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : phase_detector.vhdl
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-- File : phase_detector.vhdl
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created : 2004/12/18
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-- Created : 2004/12/18
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-- Last update :
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-- Last update :
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-- Simulators :
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-- Simulators :
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-- Synthesizers:
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-- Synthesizers:
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-- Target :
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-- Target :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description : multiply input signal with signal nco
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-- Description : multiply input signal with signal nco
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (C) 2004 Arif E. Nugroho
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-- Copyright (C) 2004 Arif E. Nugroho
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- modify it and/or implement it after contacting the author
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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-- ASSOCIATED DISCLAIMER.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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entity phase_detector is
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entity phase_detector is
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port (
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port (
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clock : in bit;
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clock : in bit;
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signal_input : in bit_vector (07 downto 0);
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signal_input : in bit_vector (07 downto 0);
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signal_nco : in bit_vector (07 downto 0);
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signal_nco : in bit_vector (07 downto 0);
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phase_output : out bit_vector (07 downto 0)
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phase_output : out bit_vector (07 downto 0)
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);
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);
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end phase_detector;
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end phase_detector;
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architecture structural of phase_detector is
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architecture structural of phase_detector is
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component mult_8bit
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component mult_8bit
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port (
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port (
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mult_01 : in bit_vector (07 downto 00);
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mult_01 : in bit_vector (07 downto 00);
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mult_02 : in bit_vector (07 downto 00);
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mult_02 : in bit_vector (07 downto 00);
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result_mult: out bit_vector (15 downto 00)
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result_mult: out bit_vector (15 downto 00)
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);
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);
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end component;
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end component;
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signal output_mult : bit_vector (15 downto 0);
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signal output_mult : bit_vector (15 downto 0);
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begin
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begin
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phase_mult: mult_8bit
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phase_mult: mult_8bit
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port map (
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port map (
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mult_01 (07 downto 0) => signal_input,
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mult_01 (07 downto 0) => signal_input,
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mult_02 (07 downto 0) => signal_nco,
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mult_02 (07 downto 0) => signal_nco,
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result_mult (15 downto 0) => output_mult
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result_mult (15 downto 0) => output_mult
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);
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);
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process (clock)
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process (clock)
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begin
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begin
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if ((clock = '1') and clock'event) then
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if ((clock = '1') and clock'event) then
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phase_output <= output_mult(15 downto 8);
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phase_output <= output_mult(15 downto 8);
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end if;
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end if;
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end process;
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end process;
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end structural;
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end structural;
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