/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OpenCores Simple General Purpose IO core ////
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//// OpenCores Simple General Purpose IO core ////
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//// ////
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//// ////
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//// Author: Richard Herveille ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// richard@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: simple_gpio.v,v 1.2 2002-12-22 16:10:17 rherveille Exp $
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// $Id: simple_gpio.v,v 1.2 2002-12-22 16:10:17 rherveille Exp $
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//
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//
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// $Date: 2002-12-22 16:10:17 $
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// $Date: 2002-12-22 16:10:17 $
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// $Revision: 1.2 $
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// $Revision: 1.2 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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//
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//
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//
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// Very basic 8bit GPIO core
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// Very basic 8bit GPIO core
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//
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//
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//
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//
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// Registers:
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// Registers:
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//
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//
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// 0x00: Control Register <io[7:0]>
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// 0x00: Control Register <io[7:0]>
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// bits 7:0 R/W Input/Output '1' = output mode
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// bits 7:0 R/W Input/Output '1' = output mode
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// '0' = input mode
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// '0' = input mode
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// 0x01: Line Register
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// 0x01: Line Register
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// bits 7:0 R Status Current GPIO pin level
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// bits 7:0 R Status Current GPIO pin level
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// W Output GPIO pin output level
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// W Output GPIO pin output level
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//
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//
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//
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//
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// HOWTO:
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// HOWTO:
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//
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//
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// Use a pin as an input:
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// Use a pin as an input:
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// Program the corresponding bit in the control register to 'input mode' ('0').
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// Program the corresponding bit in the control register to 'input mode' ('0').
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// The pin's state (input level) can be checked by reading the Line Register.
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// The pin's state (input level) can be checked by reading the Line Register.
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// Writing to the GPIO pin's Line Register bit while in input mode has no effect.
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// Writing to the GPIO pin's Line Register bit while in input mode has no effect.
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//
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//
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// Use a pin as an output:
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// Use a pin as an output:
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// Program the corresponding bit in the control register to 'output mode' ('1').
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// Program the corresponding bit in the control register to 'output mode' ('1').
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// Program the GPIO pin's output level by writing to the corresponding bit in
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// Program the GPIO pin's output level by writing to the corresponding bit in
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// the Line Register.
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// the Line Register.
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// Reading the GPIO pin's Line Register bit while in output mode returns the
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// Reading the GPIO pin's Line Register bit while in output mode returns the
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// current output level.
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// current output level.
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//
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//
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// Addapt the core for fewer GPIOs:
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// Addapt the core for fewer GPIOs:
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// If less than 8 GPIOs are required, than the 'io' parameter can be set to
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// If less than 8 GPIOs are required, than the 'io' parameter can be set to
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// the amount of required interrupts. GPIOs are mapped starting at the LSBs.
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// the amount of required interrupts. GPIOs are mapped starting at the LSBs.
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// So only the 'io' LSBs per register are valid.
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// So only the 'io' LSBs per register are valid.
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// All other bits (i.e. the 8-'io' MSBs) are set to zero '0'.
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// All other bits (i.e. the 8-'io' MSBs) are set to zero '0'.
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// Codesize is approximately linear to the amount of interrupts. I.e. using
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// Codesize is approximately linear to the amount of interrupts. I.e. using
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// 4 instead of 8 GPIO sources reduces the size by approx. half.
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// 4 instead of 8 GPIO sources reduces the size by approx. half.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module simple_gpio(
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module simple_gpio(
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clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o,
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clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o,
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gpio
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gpio
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);
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);
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//
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//
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// Inputs & outputs
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// Inputs & outputs
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//
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//
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parameter io = 8; // number of GPIOs
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parameter io = 8; // number of GPIOs
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// 8bit WISHBONE bus slave interface
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// 8bit WISHBONE bus slave interface
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input clk_i; // clock
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input clk_i; // clock
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input rst_i; // reset (asynchronous active low)
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input rst_i; // reset (asynchronous active low)
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input cyc_i; // cycle
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input cyc_i; // cycle
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input stb_i; // strobe
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input stb_i; // strobe
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input adr_i; // address adr_i[1]
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input adr_i; // address adr_i[1]
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input we_i; // write enable
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input we_i; // write enable
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input [ 7:0] dat_i; // data output
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input [ 7:0] dat_i; // data output
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output [ 7:0] dat_o; // data input
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output [ 7:0] dat_o; // data input
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output ack_o; // normal bus termination
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output ack_o; // normal bus termination
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// GPIO pins
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// GPIO pins
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inout [io:1] gpio;
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inout [io:1] gpio;
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//
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//
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// Module body
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// Module body
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//
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//
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reg [io:1] ctrl, line; // ControlRegister, LineRegister
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reg [io:1] ctrl, line; // ControlRegister, LineRegister
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reg [io:1] lgpio, llgpio; // LatchedGPIO pins
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reg [io:1] lgpio, llgpio; // LatchedGPIO pins
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//
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//
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// perform parameter checks
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// perform parameter checks
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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initial
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initial
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begin
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begin
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if(io > 8)
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if(io > 8)
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$display("simple_gpio: max. 8 GPIOs supported.");
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$display("simple_gpio: max. 8 GPIOs supported.");
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end
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end
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// synopsys translate_on
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// synopsys translate_on
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//
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//
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// WISHBONE interface
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// WISHBONE interface
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wire wb_acc = cyc_i & stb_i; // WISHBONE access
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wire wb_acc = cyc_i & stb_i; // WISHBONE access
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wire wb_wr = wb_acc & we_i; // WISHBONE write access
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wire wb_wr = wb_acc & we_i; // WISHBONE write access
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always @(posedge clk_i or negedge rst_i)
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always @(posedge clk_i or negedge rst_i)
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if (~rst_i)
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if (~rst_i)
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begin
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begin
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ctrl <= #1 {{io}{1'b0}};
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ctrl <= #1 {{io}{1'b0}};
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line <= #1 {{io}{1'b0}};
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line <= #1 {{io}{1'b0}};
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end
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end
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else if (wb_wr)
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else if (wb_wr)
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if ( adr_i )
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if ( adr_i )
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line <= #1 dat_i[io-1:0];
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line <= #1 dat_i[io-1:0];
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else
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else
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ctrl <= #1 dat_i[io-1:0];
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ctrl <= #1 dat_i[io-1:0];
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reg [7:0] dat_o;
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reg [7:0] dat_o;
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always @(posedge clk_i)
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always @(posedge clk_i)
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if ( adr_i )
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if ( adr_i )
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dat_o <= #1 { {{8-io}{1'b0}}, llgpio};
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dat_o <= #1 { {{8-io}{1'b0}}, llgpio};
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else
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else
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dat_o <= #1 { {{8-io}{1'b0}}, ctrl};
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dat_o <= #1 { {{8-io}{1'b0}}, ctrl};
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reg ack_o;
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reg ack_o;
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always @(posedge clk_i or negedge rst_i)
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always @(posedge clk_i or negedge rst_i)
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if (~rst_i)
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if (~rst_i)
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ack_o <= #1 1'b0;
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ack_o <= #1 1'b0;
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else
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else
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ack_o <= #1 wb_acc & !ack_o;
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ack_o <= #1 wb_acc & !ack_o;
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//
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//
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// GPIO section
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// GPIO section
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// latch GPIO input pins
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// latch GPIO input pins
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always @(posedge clk_i)
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always @(posedge clk_i)
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lgpio <= #1 gpio;
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lgpio <= #1 gpio;
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// latch again (reduce meta-stability risc)
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// latch again (reduce meta-stability risc)
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always @(posedge clk_i)
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always @(posedge clk_i)
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llgpio <= #1 lgpio;
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llgpio <= #1 lgpio;
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// assign GPIO outputs
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// assign GPIO outputs
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integer n;
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integer n;
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reg [io:1] igpio; // temporary internal signal
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reg [io:1] igpio; // temporary internal signal
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always @(ctrl or line)
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always @(ctrl or line)
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for(n=1;n<=io;n=n+1)
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for(n=1;n<=io;n=n+1)
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igpio[n] <= ctrl[n] ? line[n] : 1'bz;
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igpio[n] <= ctrl[n] ? line[n] : 1'bz;
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assign gpio = igpio;
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assign gpio = igpio;
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endmodule
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endmodule
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