----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Test pattern generator for the ----
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---- Test pattern generator for the ----
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---- Synchronous static RAM ("Zero Bus Turnaround" RAM, ZBT RAM) ----
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---- Synchronous static RAM ("Zero Bus Turnaround" RAM, ZBT RAM) ----
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---- simulation model. ----
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---- simulation model. ----
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---- ----
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---- ----
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---- This file is part of the simu_mem project. ----
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---- This file is part of the simu_mem project. ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- This architecture generates a random pattern. ----
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---- This architecture generates a random pattern. ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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---- - Michael Geng, vhdl@MichaelGeng.de ----
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---- - Michael Geng, vhdl@MichaelGeng.de ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2008 Authors ----
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---- Copyright (C) 2008 Authors ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
|
---- This source is distributed in the hope that it will be ----
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.gnu.org/licenses/lgpl.html ----
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---- from http://www.gnu.org/licenses/lgpl.html ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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--
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--
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ARCHITECTURE random OF patgen IS
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ARCHITECTURE random OF patgen IS
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CONSTANT D_width : INTEGER := D'LENGTH;
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CONSTANT D_width : INTEGER := D'LENGTH;
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CONSTANT A_width : INTEGER := A'LENGTH;
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CONSTANT A_width : INTEGER := A'LENGTH;
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SIGNAL next_state : state_type;
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SIGNAL next_state : state_type;
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SIGNAL state : state_type;
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SIGNAL state : state_type;
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SIGNAL last_state : state_type;
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SIGNAL last_state : state_type;
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SIGNAL next_operation : state_type;
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SIGNAL next_operation : state_type;
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SIGNAL operation : state_type;
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SIGNAL operation : state_type;
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SIGNAL want_sleep : STD_LOGIC;
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SIGNAL want_sleep : STD_LOGIC;
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SIGNAL want_sleep_delayed_1 : STD_LOGIC;
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SIGNAL want_sleep_delayed_1 : STD_LOGIC;
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SIGNAL want_sleep_delayed_2 : STD_LOGIC;
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SIGNAL want_sleep_delayed_2 : STD_LOGIC;
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SIGNAL ZZ_delayed_1 : STD_LOGIC;
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SIGNAL ZZ_delayed_1 : STD_LOGIC;
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BEGIN
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BEGIN
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ASSERT A_width >= 5
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ASSERT A_width >= 5
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REPORT "Error: Address widths < 5 bits not supported by the test pattern generator"
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REPORT "Error: Address widths < 5 bits not supported by the test pattern generator"
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SEVERITY FAILURE;
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SEVERITY FAILURE;
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D <= (D_width - 1 DOWNTO 0 => 'L');
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D <= (D_width - 1 DOWNTO 0 => 'L');
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next_state <= calc_state (CS1_n, CS2, CS2_n, WE_n, BW_n, OE_n, ADV, ZZ, operation) WHEN (CKE_n = '0');
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next_state <= calc_state (CS1_n, CS2, CS2_n, WE_n, BW_n, OE_n, ADV, ZZ, operation) WHEN (CKE_n = '0');
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next_operation <= calc_operation (next_state, operation);
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next_operation <= calc_operation (next_state, operation);
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pPatternGenerator : PROCESS (Clk, Rst) IS
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pPatternGenerator : PROCESS (Clk, Rst) IS
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VARIABLE random : NATURAL;
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VARIABLE random : NATURAL;
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VARIABLE random_u : unsigned (31 DOWNTO 0);
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VARIABLE random_u : unsigned (31 DOWNTO 0);
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VARIABLE OE_n_v : STD_LOGIC;
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VARIABLE OE_n_v : STD_LOGIC;
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VARIABLE WE_n_v : STD_LOGIC;
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VARIABLE WE_n_v : STD_LOGIC;
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VARIABLE nWE_next_rising_edge : STD_LOGIC;
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VARIABLE nWE_next_rising_edge : STD_LOGIC;
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VARIABLE ADV_v : STD_LOGIC;
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VARIABLE ADV_v : STD_LOGIC;
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VARIABLE CKE_n_v : STD_LOGIC;
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VARIABLE CKE_n_v : STD_LOGIC;
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VARIABLE nBW_v : STD_LOGIC_VECTOR (D_width / 9 - 1 DOWNTO 0);
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VARIABLE nBW_v : STD_LOGIC_VECTOR (D_width / 9 - 1 DOWNTO 0);
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VARIABLE nCS1_v : STD_LOGIC;
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VARIABLE nCS1_v : STD_LOGIC;
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VARIABLE CS2_v : STD_LOGIC;
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VARIABLE CS2_v : STD_LOGIC;
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VARIABLE nCS2_v : STD_LOGIC;
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VARIABLE nCS2_v : STD_LOGIC;
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VARIABLE ZZ_v : STD_LOGIC;
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VARIABLE ZZ_v : STD_LOGIC;
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VARIABLE State_v : state_type;
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VARIABLE State_v : state_type;
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BEGIN
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BEGIN
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IF (Rst = '1') THEN
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IF (Rst = '1') THEN
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random := 1;
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random := 1;
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WE_n_v := '0';
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WE_n_v := '0';
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D <= (D_width - 1 DOWNTO 0 => '0');
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D <= (D_width - 1 DOWNTO 0 => '0');
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A <= (A_width - 1 DOWNTO 0 => '0');
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A <= (A_width - 1 DOWNTO 0 => '0');
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ADV <= '0';
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ADV <= '0';
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WE_n <= '0';
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WE_n <= '0';
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CKE_n <= '0';
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CKE_n <= '0';
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CS1_n <= '0';
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CS1_n <= '0';
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CS2 <= '0';
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CS2 <= '0';
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CS2_n <= '0';
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CS2_n <= '0';
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CKE_n <= '0';
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CKE_n <= '0';
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OE_n <= '0';
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OE_n <= '0';
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ZZ <= '0';
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ZZ <= '0';
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ZZ_delayed_1 <= '0';
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ZZ_delayed_1 <= '0';
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LBO_n <= '0';
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LBO_n <= '0';
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BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0');
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BW_n <= (D_width / 9 - 1 DOWNTO 0 => '0');
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last_state <= Deselect;
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last_state <= Deselect;
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want_sleep <= '0';
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want_sleep <= '0';
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want_sleep_delayed_1 <= '0';
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want_sleep_delayed_1 <= '0';
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want_sleep_delayed_2 <= '0';
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want_sleep_delayed_2 <= '0';
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ELSIF RISING_EDGE (Clk) THEN
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ELSIF RISING_EDGE (Clk) THEN
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state <= next_state;
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state <= next_state;
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operation <= next_operation;
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operation <= next_operation;
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IF ((WE_n_v = '1') OR (next_state = sleep) OR (state = sleep)) THEN
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IF ((WE_n_v = '1') OR (next_state = sleep) OR (state = sleep)) THEN
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WE_n <= '1' AFTER tWH;
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WE_n <= '1' AFTER tWH;
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END IF;
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END IF;
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IF ((state = write) OR (state = write_continue)) THEN
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IF ((state = write) OR (state = write_continue)) THEN
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OE_n_v := '1';
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OE_n_v := '1';
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ELSE
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ELSE
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random := lcg (random);
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random := lcg (random);
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OE_n_v := TO_UNSIGNED (random, 32)(0);
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OE_n_v := TO_UNSIGNED (random, 32)(0);
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END IF;
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END IF;
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OE_n <= OE_n_v AFTER clk_periode - tOE;
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OE_n <= OE_n_v AFTER clk_periode - tOE;
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ELSIF FALLING_EDGE (Clk) THEN
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ELSIF FALLING_EDGE (Clk) THEN
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IF (Ena = '1') THEN
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IF (Ena = '1') THEN
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random := lcg (random);
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random := lcg (random);
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IF ((state = sleep) OR (last_state = sleep)) THEN
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IF ((state = sleep) OR (last_state = sleep)) THEN
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ADV_v := '0';
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ADV_v := '0';
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ELSE
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ELSE
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ADV_v := TO_UNSIGNED (random, 32)(0);
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ADV_v := TO_UNSIGNED (random, 32)(0);
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END IF;
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END IF;
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WE_n_v := TO_UNSIGNED (random, 32)(1);
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WE_n_v := TO_UNSIGNED (random, 32)(1);
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CKE_n_v := TO_UNSIGNED (random, 32)(2);
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CKE_n_v := TO_UNSIGNED (random, 32)(2);
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LBO_n <= TO_UNSIGNED (random, 32)(3);
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LBO_n <= TO_UNSIGNED (random, 32)(3);
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nBW_v := STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4));
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nBW_v := STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D_width / 9 + 3 DOWNTO 4));
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A <= TO_UNSIGNED (random, 32)(8) & (A_width - 5 DOWNTO 0 => '0') &
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A <= TO_UNSIGNED (random, 32)(8) & (A_width - 5 DOWNTO 0 => '0') &
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TO_UNSIGNED (random, 32)(9) & "00";
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TO_UNSIGNED (random, 32)(9) & "00";
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IF (last_state = write) OR (last_state = write_continue) THEN
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IF (last_state = write) OR (last_state = write_continue) THEN
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random_vector (D, random);
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random_vector (D, random);
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ELSE
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ELSE
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D <= (D_width - 1 DOWNTO 0 => 'Z');
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D <= (D_width - 1 DOWNTO 0 => 'Z');
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END IF;
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END IF;
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-- disable clock only about every 1024 cycles
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-- disable clock only about every 1024 cycles
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random := lcg (random);
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random := lcg (random);
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random_u := TO_UNSIGNED (random, 32);
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random_u := TO_UNSIGNED (random, 32);
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CKE_n_v := random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND
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CKE_n_v := random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND
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random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9);
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random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9);
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-- deassert CS1_n only about every 1024 cycles
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-- deassert CS1_n only about every 1024 cycles
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random := lcg (random);
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random := lcg (random);
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random_u := TO_UNSIGNED (random, 32);
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random_u := TO_UNSIGNED (random, 32);
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nCS1_v := random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND
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nCS1_v := random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND
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random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9);
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random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9);
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-- deassert CS2 only about every 1024 cycles
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-- deassert CS2 only about every 1024 cycles
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random := lcg (random);
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random := lcg (random);
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random_u := TO_UNSIGNED (random, 32);
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random_u := TO_UNSIGNED (random, 32);
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CS2_v := random_u (0) OR random_u (1) OR random_u (2) OR random_u (3) OR random_u (4) OR
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CS2_v := random_u (0) OR random_u (1) OR random_u (2) OR random_u (3) OR random_u (4) OR
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random_u (5) OR random_u (6) OR random_u (7) OR random_u (8) OR random_u (9);
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random_u (5) OR random_u (6) OR random_u (7) OR random_u (8) OR random_u (9);
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-- deassert CS2_n only about every 1024 cycles
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-- deassert CS2_n only about every 1024 cycles
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random := lcg (random);
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random := lcg (random);
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random_u := TO_UNSIGNED (random, 32);
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random_u := TO_UNSIGNED (random, 32);
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nCS2_v := random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND
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nCS2_v := random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND
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random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9);
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random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9);
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|
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-- put RAM in sleep mode only about every 1024 cycles
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-- put RAM in sleep mode only about every 1024 cycles
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random := lcg (random);
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random := lcg (random);
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random_u := TO_UNSIGNED (random, 32);
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random_u := TO_UNSIGNED (random, 32);
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want_sleep <= random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND
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want_sleep <= random_u (0) AND random_u (1) AND random_u (2) AND random_u (3) AND random_u (4) AND
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random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9);
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random_u (5) AND random_u (6) AND random_u (7) AND random_u (8) AND random_u (9);
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want_sleep_delayed_1 <= want_sleep;
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want_sleep_delayed_1 <= want_sleep;
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want_sleep_delayed_2 <= want_sleep_delayed_1;
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want_sleep_delayed_2 <= want_sleep_delayed_1;
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ZZ_v := want_sleep_delayed_2;
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ZZ_v := want_sleep_delayed_2;
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ZZ_delayed_1 <= ZZ;
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ZZ_delayed_1 <= ZZ;
|
|
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IF (WE_n = '0') AND (WE_n_v = '1') THEN
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IF (WE_n = '0') AND (WE_n_v = '1') THEN
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nWE_next_rising_edge := '0';
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nWE_next_rising_edge := '0';
|
ELSE
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ELSE
|
nWE_next_rising_edge := WE_n_v;
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nWE_next_rising_edge := WE_n_v;
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END IF;
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END IF;
|
|
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State_v := calc_state (nCS1_v, CS2_v, nCS2_v, nWE_next_rising_edge, nBW_v, OE_n, ADV_v,
|
State_v := calc_state (nCS1_v, CS2_v, nCS2_v, nWE_next_rising_edge, nBW_v, OE_n, ADV_v,
|
ZZ_v, operation);
|
ZZ_v, operation);
|
IF (State_v = invalid_state) THEN
|
IF (State_v = invalid_state) THEN
|
ADV_v := '0';
|
ADV_v := '0';
|
END IF;
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END IF;
|
|
|
State_v := calc_state (nCS1_v, CS2_v, nCS2_v, nWE_next_rising_edge, nBW_v, OE_n, ADV_v,
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State_v := calc_state (nCS1_v, CS2_v, nCS2_v, nWE_next_rising_edge, nBW_v, OE_n, ADV_v,
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ZZ_v, operation);
|
ZZ_v, operation);
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IF (State_v = invalid_state) THEN
|
IF (State_v = invalid_state) THEN
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nBW_v (0) := '0';
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nBW_v (0) := '0';
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END IF;
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END IF;
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|
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State_v := calc_state (nCS1_v, CS2_v, nCS2_v, nWE_next_rising_edge, nBW_v, OE_n, ADV_v,
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State_v := calc_state (nCS1_v, CS2_v, nCS2_v, nWE_next_rising_edge, nBW_v, OE_n, ADV_v,
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ZZ_v, operation);
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ZZ_v, operation);
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IF (((want_sleep = '1') OR (want_sleep_delayed_1 = '1') OR (want_sleep_delayed_2 = '1')) AND
|
IF (((want_sleep = '1') OR (want_sleep_delayed_1 = '1') OR (want_sleep_delayed_2 = '1')) AND
|
((State_v = write) OR (State_v = write_continue))) THEN
|
((State_v = write) OR (State_v = write_continue))) THEN
|
nCS1_v := '1';
|
nCS1_v := '1';
|
ADV_v := '0';
|
ADV_v := '0';
|
END IF;
|
END IF;
|
|
|
IF (((ZZ = '1') OR (ZZ_delayed_1 = '1')) AND
|
IF (((ZZ = '1') OR (ZZ_delayed_1 = '1')) AND
|
((State_v = write))) THEN
|
((State_v = write))) THEN
|
nCS1_v := '0';
|
nCS1_v := '0';
|
CS2_v := '1';
|
CS2_v := '1';
|
nCS2_v := '0';
|
nCS2_v := '0';
|
WE_n_v := '1';
|
WE_n_v := '1';
|
ADV_v := '0';
|
ADV_v := '0';
|
OE_n_v := '0';
|
OE_n_v := '0';
|
CKE_n_v := '0';
|
CKE_n_v := '0';
|
END IF;
|
END IF;
|
|
|
ADV <= ADV_v;
|
ADV <= ADV_v;
|
CKE_n <= CKE_n_v;
|
CKE_n <= CKE_n_v;
|
BW_n <= nBW_v;
|
BW_n <= nBW_v;
|
CKE_n <= CKE_n_v;
|
CKE_n <= CKE_n_v;
|
CS1_n <= nCS1_v;
|
CS1_n <= nCS1_v;
|
CS2 <= CS2_v;
|
CS2 <= CS2_v;
|
CS2_n <= nCS2_v;
|
CS2_n <= nCS2_v;
|
ZZ <= ZZ_v;
|
ZZ <= ZZ_v;
|
|
|
IF (WE_n_v = '0') THEN
|
IF (WE_n_v = '0') THEN
|
WE_n <= '0' AFTER clk_periode * 0.5 - tWS;
|
WE_n <= '0' AFTER clk_periode * 0.5 - tWS;
|
END IF;
|
END IF;
|
|
|
IF (CKE_n = '0') THEN
|
IF (CKE_n = '0') THEN
|
last_state <= state;
|
last_state <= state;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END IF;
|
END PROCESS pPatternGenerator;
|
END PROCESS pPatternGenerator;
|
END ARCHITECTURE random;
|
END ARCHITECTURE random;
|
|
|
