#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
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#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
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#install: C:\lscc\diamond\3.8_x64\synpbase
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#install: C:\lscc\diamond\3.8_x64\synpbase
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#OS: Windows 8 6.2
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#OS: Windows 8 6.2
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#Hostname: DESKTOP-1AUKF7V
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#Hostname: DESKTOP-1AUKF7V
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# Fri Jan 13 00:54:37 2017
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# Tue Jan 17 01:19:09 2017
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#Implementation: impl1
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#Implementation: impl1
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Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
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Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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@N|Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
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Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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@N|Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
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@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
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@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
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@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
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File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
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VHDL syntax check successful!
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VHDL syntax check successful!
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
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Compiler output is up to date. No re-compile necessary
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
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@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
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@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
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@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
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@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
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Post processing for work.rom128x1a.syn_black_box
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Post processing for work.distromasciidecoder.structure
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Post processing for work.asciidecoder.arch
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Post processing for work.displaydriverwdecoder_top.arch
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Post processing for work.displaydriverwdecoder_top.arch
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Post processing for work.displaydriverwrapper.arch
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Post processing for work.displaydriverwrapper.arch
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@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":20:8:20:13|Input button is unused.
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@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
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@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
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@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
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@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
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@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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Process completed successfully.
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# Fri Jan 13 00:54:37 2017
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# Tue Jan 17 01:19:09 2017
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###########################################################]
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###########################################################]
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Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
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Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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@N|Running in 64-bit mode
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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Process completed successfully.
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# Fri Jan 13 00:54:37 2017
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# Tue Jan 17 01:19:09 2017
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###########################################################]
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###########################################################]
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@END
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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Process completed successfully.
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# Fri Jan 13 00:54:37 2017
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# Tue Jan 17 01:19:09 2017
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###########################################################]
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###########################################################]
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Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
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Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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@N|Running in 64-bit mode
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_comp.srs changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_comp.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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Process completed successfully.
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# Fri Jan 13 00:54:39 2017
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# Tue Jan 17 01:19:11 2017
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###########################################################]
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###########################################################]
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Pre-mapping Report
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Pre-mapping Report
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Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
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Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version L-2016.03L-1
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Product Version L-2016.03L-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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@A: MF827 |No constraint file specified.
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@A: MF827 |No constraint file specified.
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@L: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt
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@L: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt
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Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt" file
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Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt" file
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@N: MF248 |Running in 64-bit mode.
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
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ICG Latch Removal Summary:
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ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
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Number of ICG latches not removed: 0
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syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
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syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Clock Summary
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Clock Summary
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*****************
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*****************
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Start Requested Requested Clock Clock Clock
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Start Requested Requested Clock Clock Clock
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Clock Frequency Period Type Group Load
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Clock Frequency Period Type Group Load
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-----------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------------
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DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8
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DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
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=====================================================================================================
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========================================================================================================
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@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":76:8:76:9|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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Finished Pre Mapping Phase.
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Finished Pre Mapping Phase.
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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None
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None
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None
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None
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Pre-mapping successful!
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Fri Jan 13 00:54:39 2017
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# Tue Jan 17 01:19:11 2017
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###########################################################]
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###########################################################]
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Map & Optimize Report
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Map & Optimize Report
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Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
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Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
Product Version L-2016.03L-1
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Product Version L-2016.03L-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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@N: MF248 |Running in 64-bit mode.
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Available hyper_sources - for debug and ip models
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Available hyper_sources - for debug and ip models
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None Found
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None Found
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@N: MT206 |Auto Constrain mode is enabled
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@N: MT206 |Auto Constrain mode is enabled
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Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
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Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
|
|
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
|
|
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
Pass CPU time Worst Slack Luts / Registers
|
Pass CPU time Worst Slack Luts / Registers
|
------------------------------------------------------------
|
------------------------------------------------------------
|
|
1 0h:00m:00s -0.70ns 1 / 8
|
|
2 0h:00m:00s -0.70ns 1 / 8
|
|
@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
|
|
Timing driven replication report
|
|
Added 1 Registers via timing driven replication
|
|
Added 0 LUTs via timing driven replication
|
|
|
|
3 0h:00m:00s -0.64ns 1 / 9
|
|
|
|
4 0h:00m:00s -0.64ns 1 / 9
|
|
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
|
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
|
|
|
|
|
|
|
@S |Clock Optimization Summary
|
@S |Clock Optimization Summary
|
|
|
|
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
|
|
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
|
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
|
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
|
|
============================== Non-Gated/Non-Generated Clocks ===============================
|
============================= Non-Gated/Non-Generated Clocks ==============================
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
---------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
@K:CKID0001 clk port 8 DDwD_Top.ascii_reg[6]
|
@K:CKID0001 button port 9 symbol_scan_cntr[0]
|
=============================================================================================
|
===========================================================================================
|
|
|
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
|
|
|
|
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
|
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
|
|
|
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
|
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
|
|
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
Writing EDIF Netlist and constraint files
|
Writing EDIF Netlist and constraint files
|
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
|
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
|
L-2016.03L-1
|
L-2016.03L-1
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
|
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
|
|
|
|
|
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
|
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
|
|
|
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"
|
@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
|
|
|
|
|
##### START OF TIMING REPORT #####[
|
##### START OF TIMING REPORT #####[
|
# Timing Report written on Fri Jan 13 00:54:42 2017
|
# Timing Report written on Tue Jan 17 01:19:13 2017
|
#
|
#
|
|
|
|
|
Top view: DisplayDriverWrapper
|
Top view: DisplayDriverWrapper
|
Requested Frequency: 1220.4 MHz
|
Requested Frequency: 443.5 MHz
|
Wire load mode: top
|
Wire load mode: top
|
Paths requested: 5
|
Paths requested: 5
|
Constraint File(s):
|
Constraint File(s):
|
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
|
|
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
|
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
|
|
|
|
|
|
|
Performance Summary
|
Performance Summary
|
*******************
|
*******************
|
|
|
|
|
Worst slack in design: -0.145
|
Worst slack in design: -0.398
|
|
|
Requested Estimated Requested Estimated Clock Clock
|
Requested Estimated Requested Estimated Clock Clock
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
------------------------------------------------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------------------------------------------
|
DisplayDriverWrapper|clk 1220.4 MHz 1037.3 MHz 0.819 0.964 -0.145 inferred Autoconstr_clkgroup_0
|
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
|
====================================================================================================================================
|
=====================================================================================================================================
|
|
|
|
|
|
|
|
|
|
|
Clock Relationships
|
Clock Relationships
|
*******************
|
*******************
|
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------------------------------------------------------
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------------------------------------------------------
|
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.819 -0.145 | No paths - | No paths - | No paths -
|
DisplayDriverWrapper|button DisplayDriverWrapper|button | 2.255 -0.398 | No paths - | No paths - | No paths -
|
===========================================================================================================================================
|
=================================================================================================================================================
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
|
|
|
|
|
|
Interface Information
|
Interface Information
|
*********************
|
*********************
|
|
|
No IO constraint found
|
No IO constraint found
|
|
|
|
|
|
|
====================================
|
====================================
|
Detailed Report for Clock: DisplayDriverWrapper|clk
|
Detailed Report for Clock: DisplayDriverWrapper|button
|
====================================
|
====================================
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
Starting Points with Worst Slack
|
********************************
|
********************************
|
|
|
Starting Arrival
|
Starting Arrival
|
Instance Reference Type Pin Net Time Slack
|
Instance Reference Type Pin Net Time Slack
|
Clock
|
Clock
|
--------------------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.753 -0.145
|
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.933 -0.398
|
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.753 -0.145
|
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398
|
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.753 -0.145
|
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.933 -0.339
|
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.753 -0.145
|
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339
|
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.753 -0.145
|
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.933 -0.280
|
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.753 -0.145
|
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280
|
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.753 -0.145
|
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277
|
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.753 -0.145
|
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570
|
==============================================================================================================
|
================================================================================================================================
|
|
|
|
|
Ending Points with Worst Slack
|
Ending Points with Worst Slack
|
******************************
|
******************************
|
|
|
Starting Required
|
Starting Required
|
Instance Reference Type Pin Net Time Slack
|
Instance Reference Type Pin Net Time Slack
|
Clock
|
Clock
|
---------------------------------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.608 -0.145
|
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398
|
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.608 -0.145
|
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339
|
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.608 -0.145
|
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339
|
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.608 -0.145
|
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 2.044 -0.280
|
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.608 -0.145
|
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 2.044 -0.280
|
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.608 -0.145
|
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100
|
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.608 -0.145
|
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100
|
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.608 -0.145
|
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
|
===============================================================================================================
|
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
|
|
==============================================================================================================================
|
|
|
|
|
|
|
Worst Path Information
|
Worst Path Information
|
***********************
|
***********************
|
|
|
|
|
Path information for path number 1:
|
Path information for path number 1:
|
Requested Period: 0.819
|
Requested Period: 2.255
|
- Setup time: 0.211
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 0.608
|
= Required time: 2.044
|
|
|
- Propagation time: 0.753
|
- Propagation time: 2.442
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : -0.145
|
= Slack (critical) : -0.398
|
|
|
Number of logic level(s): 0
|
Number of logic level(s): 4
|
Starting point: DDwD_Top.ascii_reg[0] / Q
|
Starting point: symbol_scan_cntr[1] / Q
|
Ending point: DDwD_Top.ascii_reg[0] / D
|
Ending point: symbol_scan_cntr[7] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.753 0.753 -
|
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
|
ascii_reg[0] Net - - - - 1
|
symbol_scan_cntr[1] Net - - - - 15
|
DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.753 -
|
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
|
=======================================================================================
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
|
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
|
|
===========================================================================================
|
|
|
|
|
Path information for path number 2:
|
Path information for path number 2:
|
Requested Period: 0.819
|
Requested Period: 2.255
|
- Setup time: 0.211
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 0.608
|
= Required time: 2.044
|
|
|
- Propagation time: 0.753
|
- Propagation time: 2.442
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : -0.145
|
= Slack (critical) : -0.398
|
|
|
Number of logic level(s): 0
|
Number of logic level(s): 4
|
Starting point: DDwD_Top.ascii_reg[1] / Q
|
Starting point: symbol_scan_cntr[2] / Q
|
Ending point: DDwD_Top.ascii_reg[1] / D
|
Ending point: symbol_scan_cntr[7] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.753 0.753 -
|
symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -
|
ascii_reg[1] Net - - - - 1
|
symbol_scan_cntr[2] Net - - - - 15
|
DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.753 -
|
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
|
=======================================================================================
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
|
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
|
|
===========================================================================================
|
|
|
|
|
Path information for path number 3:
|
Path information for path number 3:
|
Requested Period: 0.819
|
Requested Period: 2.255
|
- Setup time: 0.211
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 0.608
|
= Required time: 2.044
|
|
|
- Propagation time: 0.753
|
- Propagation time: 2.382
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : -0.145
|
= Slack (non-critical) : -0.339
|
|
|
Number of logic level(s): 0
|
Number of logic level(s): 3
|
Starting point: DDwD_Top.ascii_reg[2] / Q
|
Starting point: symbol_scan_cntr[3] / Q
|
Ending point: DDwD_Top.ascii_reg[2] / D
|
Ending point: symbol_scan_cntr[7] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.753 0.753 -
|
symbol_scan_cntr[3] FD1S3DX Q Out 0.933 0.933 -
|
ascii_reg[2] Net - - - - 1
|
symbol_scan_cntr[3] Net - - - - 15
|
DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.753 -
|
symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -
|
=======================================================================================
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
|
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
|
|
===========================================================================================
|
|
|
|
|
Path information for path number 4:
|
Path information for path number 4:
|
Requested Period: 0.819
|
Requested Period: 2.255
|
- Setup time: 0.211
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 0.608
|
= Required time: 2.044
|
|
|
- Propagation time: 0.753
|
- Propagation time: 2.382
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : -0.145
|
= Slack (non-critical) : -0.339
|
|
|
Number of logic level(s): 0
|
Number of logic level(s): 3
|
Starting point: DDwD_Top.ascii_reg[3] / Q
|
Starting point: symbol_scan_cntr[4] / Q
|
Ending point: DDwD_Top.ascii_reg[3] / D
|
Ending point: symbol_scan_cntr[7] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.753 0.753 -
|
symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -
|
ascii_reg[3] Net - - - - 1
|
symbol_scan_cntr[4] Net - - - - 15
|
DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.753 -
|
symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -
|
=======================================================================================
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
|
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
|
|
===========================================================================================
|
|
|
|
|
Path information for path number 5:
|
Path information for path number 5:
|
Requested Period: 0.819
|
Requested Period: 2.255
|
- Setup time: 0.211
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 0.608
|
= Required time: 2.044
|
|
|
- Propagation time: 0.753
|
- Propagation time: 2.382
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : -0.145
|
= Slack (non-critical) : -0.339
|
|
|
Number of logic level(s): 0
|
Number of logic level(s): 3
|
Starting point: DDwD_Top.ascii_reg[4] / Q
|
Starting point: symbol_scan_cntr[1] / Q
|
Ending point: DDwD_Top.ascii_reg[4] / D
|
Ending point: symbol_scan_cntr[5] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.753 0.753 -
|
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
|
ascii_reg[4] Net - - - - 1
|
symbol_scan_cntr[1] Net - - - - 15
|
DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.753 -
|
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
|
=======================================================================================
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
|
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -
|
|
symbol_scan_cntr_s[5] Net - - - - 1
|
|
symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -
|
|
===========================================================================================
|
|
|
|
|
|
|
##### END OF TIMING REPORT #####]
|
##### END OF TIMING REPORT #####]
|
|
|
Constraints that could not be applied
|
Constraints that could not be applied
|
None
|
None
|
|
|
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
|
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
|
|
|
|
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
|
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
|
|
---------------------------------------
|
---------------------------------------
|
Resource Usage Report
|
Resource Usage Report
|
Part: lfe5um5g_45f-8
|
Part: lfe5um5g_45f-8
|
|
|
Register bits: 8 of 43848 (0%)
|
Register bits: 9 of 43848 (0%)
|
PIC Latch: 0
|
PIC Latch: 0
|
I/O cells: 18
|
I/O cells: 18
|
|
|
|
|
Details:
|
Details:
|
FD1S3IX: 5
|
CCU2C: 5
|
FD1S3JX: 3
|
FD1S3DX: 9
|
GSR: 1
|
GSR: 1
|
IB: 2
|
IB: 2
|
|
INV: 1
|
OB: 16
|
OB: 16
|
PUR: 1
|
PUR: 1
|
VHI: 2
|
ROM128X1A: 14
|
|
VHI: 1
|
VLO: 1
|
VLO: 1
|
false: 1
|
|
Mapper successful!
|
Mapper successful!
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)
|
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
|
|
|
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
# Fri Jan 13 00:54:42 2017
|
# Tue Jan 17 01:19:13 2017
|
|
|
###########################################################]
|
###########################################################]
|
|
|
