Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
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Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version L-2016.03L-1
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Product Version L-2016.03L-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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@N: MF248 |Running in 64-bit mode.
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Available hyper_sources - for debug and ip models
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Available hyper_sources - for debug and ip models
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None Found
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None Found
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@N: MT206 |Auto Constrain mode is enabled
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@N: MT206 |Auto Constrain mode is enabled
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Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":77:4:77:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
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@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":77:4:77:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
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Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Pass CPU time Worst Slack Luts / Registers
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Pass CPU time Worst Slack Luts / Registers
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------------------------------------------------------------
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------------------------------------------------------------
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1 0h:00m:00s -0.76ns 6 / 13
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1 0h:00m:00s -0.76ns 6 / 13
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2 0h:00m:00s -0.76ns 6 / 13
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2 0h:00m:00s -0.76ns 6 / 13
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3 0h:00m:00s -0.62ns 7 / 13
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3 0h:00m:00s -0.62ns 7 / 13
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4 0h:00m:00s -0.58ns 6 / 13
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4 0h:00m:00s -0.58ns 6 / 13
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Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
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@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
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Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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@N: MT611 :|Automatically generated clock DisplayDriverWrapper|bttn_state_derived_clock is not used and is being removed
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@N: MT611 :|Automatically generated clock DisplayDriverWrapper|bttn_state_derived_clock is not used and is being removed
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@S |Clock Optimization Summary
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@S |Clock Optimization Summary
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#### START OF CLOCK OPTIMIZATION REPORT #####[
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#### START OF CLOCK OPTIMIZATION REPORT #####[
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1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
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1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
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0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
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0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
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8 instances converted, 0 sequential instances remain driven by gated/generated clocks
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8 instances converted, 0 sequential instances remain driven by gated/generated clocks
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=========================== Non-Gated/Non-Generated Clocks ============================
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=========================== Non-Gated/Non-Generated Clocks ============================
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Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
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Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
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---------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------
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@K:CKID0001 clk port 13 bttn_state
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@K:CKID0001 clk port 13 bttn_state
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=======================================================================================
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=======================================================================================
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##### END OF CLOCK OPTIMIZATION REPORT ######]
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##### END OF CLOCK OPTIMIZATION REPORT ######]
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Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
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Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
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Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm
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Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm
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Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Writing EDIF Netlist and constraint files
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Writing EDIF Netlist and constraint files
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@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
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@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
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L-2016.03L-1
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L-2016.03L-1
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@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
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@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
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Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
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Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
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Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
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Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
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@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
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@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
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##### START OF TIMING REPORT #####[
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##### START OF TIMING REPORT #####[
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# Timing Report written on Tue Jan 17 01:29:40 2017
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# Timing Report written on Tue Jan 17 23:41:24 2017
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#
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#
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Top view: DisplayDriverWrapper
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Top view: DisplayDriverWrapper
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Requested Frequency: 433.9 MHz
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Requested Frequency: 433.9 MHz
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Wire load mode: top
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Wire load mode: top
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Paths requested: 5
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Paths requested: 5
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Constraint File(s):
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Constraint File(s):
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@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
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@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
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@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
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@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
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Performance Summary
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Performance Summary
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*******************
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*******************
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Worst slack in design: -0.407
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Worst slack in design: -0.407
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Requested Estimated Requested Estimated Clock Clock
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Requested Estimated Requested Estimated Clock Clock
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Starting Clock Frequency Frequency Period Period Slack Type Group
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Starting Clock Frequency Frequency Period Period Slack Type Group
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----------------------------------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------------------------------
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DisplayDriverWrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
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DisplayDriverWrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
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==================================================================================================================================
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==================================================================================================================================
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Clock Relationships
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Clock Relationships
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*******************
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*******************
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Clocks | rise to rise | fall to fall | rise to fall | fall to rise
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Clocks | rise to rise | fall to fall | rise to fall | fall to rise
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-------------------------------------------------------------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------------------------------------------------------------
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Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
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Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
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-------------------------------------------------------------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------------------------------------------------------------
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DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
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DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
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===========================================================================================================================================
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===========================================================================================================================================
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Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
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Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
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'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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Interface Information
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Interface Information
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*********************
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*********************
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No IO constraint found
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No IO constraint found
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====================================
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====================================
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Detailed Report for Clock: DisplayDriverWrapper|clk
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Detailed Report for Clock: DisplayDriverWrapper|clk
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====================================
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====================================
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Starting Points with Worst Slack
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Starting Points with Worst Slack
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********************************
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********************************
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Starting Arrival
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Starting Arrival
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Instance Reference Type Pin Net Time Slack
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Instance Reference Type Pin Net Time Slack
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Clock
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Clock
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-------------------------------------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------------------------------------
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symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407
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symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407
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symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
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symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
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symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348
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symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348
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symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
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symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
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symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289
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symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289
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symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
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symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
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symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
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symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
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bttn_state_fifo[3] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
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bttn_state_fifo[3] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
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bttn_state DisplayDriverWrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
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bttn_state DisplayDriverWrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
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bttn_state_fifo[1] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606
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bttn_state_fifo[1] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606
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===================================================================================================================
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===================================================================================================================
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Ending Points with Worst Slack
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Ending Points with Worst Slack
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******************************
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******************************
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Starting Required
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Starting Required
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Instance Reference Type Pin Net Time Slack
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Instance Reference Type Pin Net Time Slack
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Clock
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Clock
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--------------------------------------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------------------------------------
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symbol_scan_cntr[7] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
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symbol_scan_cntr[7] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
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symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348
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symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348
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symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348
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symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348
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symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
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symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
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symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
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symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
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symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
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symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
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symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
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symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
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symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
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symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
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symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
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symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
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symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
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symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
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================================================================================================================================
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================================================================================================================================
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Worst Path Information
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Worst Path Information
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***********************
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***********************
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Path information for path number 1:
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Path information for path number 1:
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Requested Period: 2.305
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Requested Period: 2.305
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- Setup time: 0.211
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- Setup time: 0.211
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+ Clock delay at ending point: 0.000 (ideal)
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+ Clock delay at ending point: 0.000 (ideal)
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= Required time: 2.094
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= Required time: 2.094
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- Propagation time: 2.501
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- Propagation time: 2.501
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- Clock delay at starting point: 0.000 (ideal)
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- Clock delay at starting point: 0.000 (ideal)
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= Slack (critical) : -0.407
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= Slack (critical) : -0.407
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Number of logic level(s): 5
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Number of logic level(s): 5
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Starting point: symbol_scan_cntr[0] / Q
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Starting point: symbol_scan_cntr[0] / Q
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Ending point: symbol_scan_cntr[7] / D
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Ending point: symbol_scan_cntr[7] / D
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The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
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The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
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The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
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The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
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Instance / Net Pin Pin Arrival No. of
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
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Name Type Name Dir Delay Time Fan Out(s)
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-------------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------------
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symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
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symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
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symbol_scan_cntr[0] Net - - - - 15
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symbol_scan_cntr[0] Net - - - - 15
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symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
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symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
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symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
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symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
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symbol_scan_cntr_cry[0] Net - - - - 1
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symbol_scan_cntr_cry[0] Net - - - - 1
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
|
symbol_scan_cntr_s[7] Net - - - - 1
|
symbol_scan_cntr_s[7] Net - - - - 1
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -
|
===========================================================================================
|
===========================================================================================
|
|
|
|
|
Path information for path number 2:
|
Path information for path number 2:
|
Requested Period: 2.305
|
Requested Period: 2.305
|
- Setup time: 0.211
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 2.094
|
= Required time: 2.094
|
|
|
- Propagation time: 2.442
|
- Propagation time: 2.442
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (non-critical) : -0.348
|
= Slack (non-critical) : -0.348
|
|
|
Number of logic level(s): 4
|
Number of logic level(s): 4
|
Starting point: symbol_scan_cntr[1] / Q
|
Starting point: symbol_scan_cntr[1] / Q
|
Ending point: symbol_scan_cntr[7] / D
|
Ending point: symbol_scan_cntr[7] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
-------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
|
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
|
symbol_scan_cntr[1] Net - - - - 15
|
symbol_scan_cntr[1] Net - - - - 15
|
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
|
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
symbol_scan_cntr_s[7] Net - - - - 1
|
symbol_scan_cntr_s[7] Net - - - - 1
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
===========================================================================================
|
===========================================================================================
|
|
|
|
|
Path information for path number 3:
|
Path information for path number 3:
|
Requested Period: 2.305
|
Requested Period: 2.305
|
- Setup time: 0.211
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 2.094
|
= Required time: 2.094
|
|
|
- Propagation time: 2.442
|
- Propagation time: 2.442
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (non-critical) : -0.348
|
= Slack (non-critical) : -0.348
|
|
|
Number of logic level(s): 4
|
Number of logic level(s): 4
|
Starting point: symbol_scan_cntr[2] / Q
|
Starting point: symbol_scan_cntr[2] / Q
|
Ending point: symbol_scan_cntr[7] / D
|
Ending point: symbol_scan_cntr[7] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
-------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
|
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
|
symbol_scan_cntr[2] Net - - - - 15
|
symbol_scan_cntr[2] Net - - - - 15
|
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
|
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
symbol_scan_cntr_s[7] Net - - - - 1
|
symbol_scan_cntr_s[7] Net - - - - 1
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
===========================================================================================
|
===========================================================================================
|
|
|
|
|
Path information for path number 4:
|
Path information for path number 4:
|
Requested Period: 2.305
|
Requested Period: 2.305
|
- Setup time: 0.211
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 2.094
|
= Required time: 2.094
|
|
|
- Propagation time: 2.442
|
- Propagation time: 2.442
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (non-critical) : -0.348
|
= Slack (non-critical) : -0.348
|
|
|
Number of logic level(s): 4
|
Number of logic level(s): 4
|
Starting point: symbol_scan_cntr[0] / Q
|
Starting point: symbol_scan_cntr[0] / Q
|
Ending point: symbol_scan_cntr[5] / D
|
Ending point: symbol_scan_cntr[5] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
-------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
symbol_scan_cntr[0] Net - - - - 15
|
symbol_scan_cntr[0] Net - - - - 15
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
|
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
|
symbol_scan_cntr_s[5] Net - - - - 1
|
symbol_scan_cntr_s[5] Net - - - - 1
|
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
|
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
|
===========================================================================================
|
===========================================================================================
|
|
|
|
|
Path information for path number 5:
|
Path information for path number 5:
|
Requested Period: 2.305
|
Requested Period: 2.305
|
- Setup time: 0.211
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 2.094
|
= Required time: 2.094
|
|
|
- Propagation time: 2.442
|
- Propagation time: 2.442
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (non-critical) : -0.348
|
= Slack (non-critical) : -0.348
|
|
|
Number of logic level(s): 4
|
Number of logic level(s): 4
|
Starting point: symbol_scan_cntr[0] / Q
|
Starting point: symbol_scan_cntr[0] / Q
|
Ending point: symbol_scan_cntr[6] / D
|
Ending point: symbol_scan_cntr[6] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
-------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
symbol_scan_cntr[0] Net - - - - 15
|
symbol_scan_cntr[0] Net - - - - 15
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
|
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
|
symbol_scan_cntr_s[6] Net - - - - 1
|
symbol_scan_cntr_s[6] Net - - - - 1
|
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
|
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
|
===========================================================================================
|
===========================================================================================
|
|
|
|
|
|
|
##### END OF TIMING REPORT #####]
|
##### END OF TIMING REPORT #####]
|
|
|
Constraints that could not be applied
|
Constraints that could not be applied
|
None
|
None
|
|
|
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
|
|
|
|
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
|
|
---------------------------------------
|
---------------------------------------
|
Resource Usage Report
|
Resource Usage Report
|
Part: lfe5um5g_45f-8
|
Part: lfe5um5g_45f-8
|
|
|
Register bits: 13 of 43848 (0%)
|
Register bits: 13 of 43848 (0%)
|
PIC Latch: 0
|
PIC Latch: 0
|
I/O cells: 19
|
I/O cells: 19
|
|
|
|
|
Details:
|
Details:
|
CCU2C: 5
|
CCU2C: 5
|
FD1P3DX: 8
|
FD1P3DX: 8
|
FD1S3AX: 1
|
FD1S3AX: 1
|
FD1S3JX: 3
|
FD1S3JX: 3
|
GSR: 1
|
GSR: 1
|
IB: 3
|
IB: 3
|
IFS1P3JX: 1
|
IFS1P3JX: 1
|
INV: 2
|
INV: 2
|
OB: 16
|
OB: 16
|
ORCALUT4: 4
|
ORCALUT4: 4
|
PUR: 1
|
PUR: 1
|
ROM128X1A: 14
|
ROM128X1A: 14
|
VHI: 1
|
VHI: 1
|
VLO: 1
|
VLO: 1
|
Mapper successful!
|
Mapper successful!
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
|
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
|
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
# Tue Jan 17 01:29:40 2017
|
# Tue Jan 17 23:41:24 2017
|
|
|
###########################################################]
|
###########################################################]
|
|
|
