-- $Author: rpaley_yid $
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-- $Author: rpaley_yid $
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-- $Date: 2003-01-14 21:48:11 $
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-- $Date: 2003-01-14 21:48:11 $
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-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/tb_single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
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-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/tb_single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
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-- $Locker
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-- $Locker
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-- $Revision: 1.1.1.1 $
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-- $Revision: 1.1.1.1 $
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-- $State: Exp $
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-- $State: Exp $
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-- --------------------------------------------------------------------------
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-- --------------------------------------------------------------------------
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--
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--
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-- Purpose: This file specifies test bench harness for the single_port
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-- Purpose: This file specifies test bench harness for the single_port
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-- Memory. It also contains the configuration files for all the
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-- Memory. It also contains the configuration files for all the
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-- tests.
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-- tests.
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--
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--
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--
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--
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-- References:
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-- References:
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-- 1. The Designer's Guide to VHDL by Peter Ashenden
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-- 1. The Designer's Guide to VHDL by Peter Ashenden
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-- ISBN: 1-55860-270-4 (pbk.)
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-- ISBN: 1-55860-270-4 (pbk.)
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-- 2. Writing Testbenches - Functional Verification of HDL models by
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-- 2. Writing Testbenches - Functional Verification of HDL models by
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-- Janick Bergeron | ISBN: 0-7923-7766-4
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-- Janick Bergeron | ISBN: 0-7923-7766-4
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--
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--
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-- Notes:
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-- Notes:
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--
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--
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-- --------------------------------------------------------------------------
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-- --------------------------------------------------------------------------
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LIBRARY IEEE;
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LIBRARY IEEE;
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LIBRARY WORK;
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LIBRARY WORK;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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USE WORK.linked_list_mem_pkg.ALL;
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USE WORK.linked_list_mem_pkg.ALL;
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USE WORK.single_port_pkg.all;
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USE WORK.single_port_pkg.all;
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USE STD.TEXTIO.ALL;
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USE STD.TEXTIO.ALL;
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ENTITY tb_single_port IS
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ENTITY tb_single_port IS
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END ENTITY tb_single_port;
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END ENTITY tb_single_port;
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ARCHITECTURE BHV of tb_single_port IS
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ARCHITECTURE BHV of tb_single_port IS
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COMPONENT single_port IS
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COMPONENT single_port IS
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GENERIC (
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GENERIC (
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rnwtQ : TIME := 1 NS
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rnwtQ : TIME := 1 NS
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);
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);
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PORT (
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PORT (
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d : IN data_inter_typ;
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d : IN data_inter_typ;
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q : OUT data_inter_typ;
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q : OUT data_inter_typ;
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a : IN addr_inter_typ;
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a : IN addr_inter_typ;
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rnw : IN STD_LOGIC;
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rnw : IN STD_LOGIC;
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dealloc_mem : BOOLEAN
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dealloc_mem : BOOLEAN
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);
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);
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END COMPONENT single_port;
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END COMPONENT single_port;
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COMPONENT tc_single_port IS
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COMPONENT tc_single_port IS
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PORT (
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PORT (
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to_srv : OUT to_srv_typ;
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to_srv : OUT to_srv_typ;
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frm_srv : IN frm_srv_typ
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frm_srv : IN frm_srv_typ
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);
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);
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END COMPONENT tc_single_port;
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END COMPONENT tc_single_port;
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SIGNAL d : data_inter_typ;
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SIGNAL d : data_inter_typ;
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SIGNAL q : data_inter_typ;
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SIGNAL q : data_inter_typ;
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SIGNAL a : addr_inter_typ;
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SIGNAL a : addr_inter_typ;
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SIGNAL rnw : STD_LOGIC;
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SIGNAL rnw : STD_LOGIC;
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SIGNAL dealloc_mem : BOOLEAN;
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SIGNAL dealloc_mem : BOOLEAN;
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SIGNAL to_srv : to_srv_typ;
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SIGNAL to_srv : to_srv_typ;
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SIGNAL frm_srv : frm_srv_typ;
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SIGNAL frm_srv : frm_srv_typ;
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SIGNAL tie_vdd : STD_LOGIC := '1';
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SIGNAL tie_vdd : STD_LOGIC := '1';
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BEGIN
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BEGIN
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dut : single_port
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dut : single_port
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PORT MAP (
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PORT MAP (
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d => d,
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d => d,
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a => a,
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a => a,
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q => q,
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q => q,
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rnw => rnw,
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rnw => rnw,
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dealloc_mem => dealloc_mem
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dealloc_mem => dealloc_mem
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);
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);
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tc : tc_single_port
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tc : tc_single_port
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PORT MAP (
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PORT MAP (
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to_srv => to_srv,
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to_srv => to_srv,
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frm_srv => frm_srv
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frm_srv => frm_srv
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);
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);
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single_port_server : PROCESS
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single_port_server : PROCESS
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VARIABLE frm_srv_v : frm_srv_typ;
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VARIABLE frm_srv_v : frm_srv_typ;
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CONSTANT ACCESS_DELAY : TIME := 5 NS;
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CONSTANT ACCESS_DELAY : TIME := 5 NS;
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BEGIN
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BEGIN
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-- Wait until the test case is finished setting up the next memory access.
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-- Wait until the test case is finished setting up the next memory access.
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WAIT ON to_srv'TRANSACTION;
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WAIT ON to_srv'TRANSACTION;
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CASE to_srv.do IS
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CASE to_srv.do IS
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WHEN init =>
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WHEN init =>
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ASSERT FALSE
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ASSERT FALSE
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REPORT "initialized"
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REPORT "initialized"
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SEVERITY NOTE;
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SEVERITY NOTE;
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WHEN read => -- perform memory read
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WHEN read => -- perform memory read
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d <= to_srv.data;
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d <= to_srv.data;
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a <= to_srv.addr;
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a <= to_srv.addr;
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rnw <= '1';
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rnw <= '1';
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-- Wait for data to appear
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-- Wait for data to appear
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WAIT FOR ACCESS_DELAY;
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WAIT FOR ACCESS_DELAY;
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WHEN write => -- perform memory write
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WHEN write => -- perform memory write
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d <= to_srv.data;
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d <= to_srv.data;
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a <= to_srv.addr;
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a <= to_srv.addr;
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rnw <= '0';
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rnw <= '0';
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WAIT FOR ACCESS_DELAY;
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WAIT FOR ACCESS_DELAY;
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WHEN dealloc => -- deallocate the linked list for the LL architecture
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WHEN dealloc => -- deallocate the linked list for the LL architecture
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dealloc_mem <= true;
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dealloc_mem <= true;
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WHEN end_test => -- reached the end of the test case
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WHEN end_test => -- reached the end of the test case
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WAIT;
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WAIT;
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END CASE;
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END CASE;
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frm_srv_v.data := q;
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frm_srv_v.data := q;
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-- Send message to test case to continue the test.
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-- Send message to test case to continue the test.
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frm_srv <= frm_srv_v ; WAIT FOR 0 NS;
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frm_srv <= frm_srv_v ; WAIT FOR 0 NS;
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END PROCESS single_port_server;
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END PROCESS single_port_server;
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END BHV;
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END BHV;
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CONFIGURATION ll_main_cfg OF TB_SINGLE_PORT IS
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CONFIGURATION ll_main_cfg OF TB_SINGLE_PORT IS
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FOR BHV
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FOR BHV
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FOR dut : single_port
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FOR dut : single_port
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USE ENTITY work.single_port(LinkedList);
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USE ENTITY work.single_port(LinkedList);
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END FOR; -- dut
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END FOR; -- dut
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FOR tc : tc_single_port
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FOR tc : tc_single_port
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USE ENTITY work.tc_single_port(TC0);
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USE ENTITY work.tc_single_port(TC0);
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END FOR; -- tc;
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END FOR; -- tc;
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END FOR; -- BHV
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END FOR; -- BHV
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END CONFIGURATION ll_main_cfg;
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END CONFIGURATION ll_main_cfg;
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CONFIGURATION ll_error_cfg OF TB_SINGLE_PORT IS
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CONFIGURATION ll_error_cfg OF TB_SINGLE_PORT IS
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FOR BHV
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FOR BHV
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FOR dut : single_port
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FOR dut : single_port
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USE ENTITY work.single_port(LinkedList);
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USE ENTITY work.single_port(LinkedList);
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END FOR; -- dut
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END FOR; -- dut
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FOR tc : tc_single_port
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FOR tc : tc_single_port
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USE ENTITY work.tc_single_port(TC1);
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USE ENTITY work.tc_single_port(TC1);
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END FOR; -- tc;
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END FOR; -- tc;
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END FOR; -- BHV
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END FOR; -- BHV
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END CONFIGURATION ll_error_cfg ;
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END CONFIGURATION ll_error_cfg ;
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CONFIGURATION mem_main_cfg of TB_SINGLE_PORT IS
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CONFIGURATION mem_main_cfg of TB_SINGLE_PORT IS
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FOR BHV
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FOR BHV
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FOR dut : single_port
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FOR dut : single_port
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USE ENTITY work.single_port(ArrayMem);
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USE ENTITY work.single_port(ArrayMem);
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END FOR; -- dut
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END FOR; -- dut
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FOR tc : tc_single_port
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FOR tc : tc_single_port
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USE ENTITY work.tc_single_port(TC0);
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USE ENTITY work.tc_single_port(TC0);
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END FOR; -- tc;
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END FOR; -- tc;
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END FOR; -- BHV
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END FOR; -- BHV
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END CONFIGURATION mem_main_cfg;
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END CONFIGURATION mem_main_cfg;
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CONFIGURATION mem_error_cfg of TB_SINGLE_PORT IS
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CONFIGURATION mem_error_cfg of TB_SINGLE_PORT IS
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FOR BHV
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FOR BHV
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FOR dut : single_port
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FOR dut : single_port
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USE ENTITY work.single_port(ArrayMem);
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USE ENTITY work.single_port(ArrayMem);
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END FOR; -- dut
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END FOR; -- dut
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FOR tc : tc_single_port
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FOR tc : tc_single_port
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USE ENTITY work.tc_single_port(TC1);
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USE ENTITY work.tc_single_port(TC1);
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END FOR; -- tc;
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END FOR; -- tc;
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END FOR; -- BHV
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END FOR; -- BHV
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END CONFIGURATION mem_error_cfg;
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END CONFIGURATION mem_error_cfg;
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CONFIGURATION memnoflag_main_cfg of TB_SINGLE_PORT IS
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CONFIGURATION memnoflag_main_cfg of TB_SINGLE_PORT IS
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FOR BHV
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FOR BHV
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FOR dut : single_port
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FOR dut : single_port
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USE ENTITY work.single_port(ArrayMemNoFlag);
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USE ENTITY work.single_port(ArrayMemNoFlag);
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END FOR; -- dut
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END FOR; -- dut
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FOR tc : tc_single_port
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FOR tc : tc_single_port
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USE ENTITY work.tc_single_port(TC0);
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USE ENTITY work.tc_single_port(TC0);
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END FOR; -- tc;
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END FOR; -- tc;
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END FOR; -- BHV
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END FOR; -- BHV
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END CONFIGURATION memnoflag_main_cfg;
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END CONFIGURATION memnoflag_main_cfg;
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CONFIGURATION memnoflag_error_cfg of TB_SINGLE_PORT IS
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CONFIGURATION memnoflag_error_cfg of TB_SINGLE_PORT IS
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FOR BHV
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FOR BHV
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FOR dut : single_port
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FOR dut : single_port
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USE ENTITY work.single_port(ArrayMemNoFlag);
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USE ENTITY work.single_port(ArrayMemNoFlag);
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END FOR; -- dut
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END FOR; -- dut
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FOR tc : tc_single_port
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FOR tc : tc_single_port
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USE ENTITY work.tc_single_port(TC1);
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USE ENTITY work.tc_single_port(TC1);
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END FOR; -- tc;
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END FOR; -- tc;
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END FOR; -- BHV
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END FOR; -- BHV
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END CONFIGURATION memnoflag_error_cfg;
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END CONFIGURATION memnoflag_error_cfg;
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1 2003/01/14 17:49:04 Default
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-- Revision 1.1 2003/01/14 17:49:04 Default
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-- Initial revision
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-- Initial revision
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--
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--
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-- Revision 1.2 2002/12/31 19:19:43 Default
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-- Revision 1.2 2002/12/31 19:19:43 Default
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-- Updated 'transaction statements for fixed simulator.
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-- Updated 'transaction statements for fixed simulator.
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--
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--
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-- Revision 1.1 2002/12/24 18:10:18 Default
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-- Revision 1.1 2002/12/24 18:10:18 Default
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-- Initial revision
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-- Initial revision
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--
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--
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