----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Single port asynchronous RAM simulation model ----
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---- Single port asynchronous RAM simulation model ----
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---- ----
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---- ----
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---- This file is part of the single_port project ----
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---- This file is part of the single_port project ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- This package implements functions to allocate, write, read ----
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---- This package implements functions to allocate, write, read ----
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---- and deallocate a linked list based memory. ----
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---- and deallocate a linked list based memory. ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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---- - Robert Paley, rpaley_yid@yahoo.com ----
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---- - Robert Paley, rpaley_yid@yahoo.com ----
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---- - Michael Geng, vhdl@MichaelGeng.de ----
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---- - Michael Geng, vhdl@MichaelGeng.de ----
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---- ----
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---- ----
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---- References: ----
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---- References: ----
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---- 1. The Designer's Guide to VHDL by Peter Ashenden ----
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---- 1. The Designer's Guide to VHDL by Peter Ashenden ----
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---- ISBN: 1-55860-270-4 (pbk.) ----
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---- ISBN: 1-55860-270-4 (pbk.) ----
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---- 2. Writing Testbenches - Functional Verification of HDL ----
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---- 2. Writing Testbenches - Functional Verification of HDL ----
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---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
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---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2005 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2005 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2005/10/12 19:39:27 mgeng
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-- Revision 1.2 2005/10/12 19:39:27 mgeng
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-- Buses unconstrained, LGPL header added
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-- Buses unconstrained, LGPL header added
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--
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--
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-- Revision 1.1.1.1 2003/01/14 21:48:10 rpaley_yid
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-- Revision 1.1.1.1 2003/01/14 21:48:10 rpaley_yid
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-- initial checkin
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-- initial checkin
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--
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--
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-- Revision 1.1 2003/01/14 17:47:32 Default
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-- Revision 1.1 2003/01/14 17:47:32 Default
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-- Initial revision
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-- Initial revision
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--
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--
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-- Revision 1.1 2002/12/24 18:03:50 Default
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-- Revision 1.1 2002/12/24 18:03:50 Default
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-- Initial revision
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-- Initial revision
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--
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--
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LIBRARY IEEE;
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LIBRARY IEEE;
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LIBRARY WORK;
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LIBRARY WORK;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE WORK.single_port_pkg.all;
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USE WORK.single_port_pkg.all;
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|
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PACKAGE linked_list_mem_pkg IS
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PACKAGE linked_list_mem_pkg IS
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CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth
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CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth
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-- pointer to one data word in the memory
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-- pointer to one data word in the memory
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-- The reason for using a pointer here is that it seems to be the only way to keep the model
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-- The reason for using a pointer here is that it seems to be the only way to keep the model
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-- independent of the data width
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-- independent of the data width
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TYPE data_ptr IS ACCESS BIT_VECTOR;
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TYPE data_ptr IS ACCESS BIT_VECTOR;
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-- data memory array type definition
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-- data memory array type definition
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TYPE mem_array_typ IS ARRAY (0 TO PAGEDEPTH-1) OF data_ptr;
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TYPE mem_array_typ IS ARRAY (0 TO PAGEDEPTH-1) OF data_ptr;
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-- Define memory page linked list cell. This cell contains
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-- Define memory page linked list cell. This cell contains
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-- the mem_array, starting page address, valid data array and
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-- the mem_array, starting page address, valid data array and
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-- the pointer to the next element in the linked list.
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-- the pointer to the next element in the linked list.
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TYPE mem_page_typ;
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TYPE mem_page_typ;
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-- pointer to next item in the linked list.
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-- pointer to next item in the linked list.
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TYPE mem_page_ptr IS ACCESS mem_page_typ;
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TYPE mem_page_ptr IS ACCESS mem_page_typ;
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TYPE mem_page_typ IS RECORD
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TYPE mem_page_typ IS RECORD
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mem_array : mem_array_typ; -- data memory
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mem_array : mem_array_typ; -- data memory
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page_address : addr_typ;
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page_address : addr_typ;
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next_cell : mem_page_ptr;
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next_cell : mem_page_ptr;
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END RECORD mem_page_typ;
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END RECORD mem_page_typ;
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PROCEDURE rw_mem (
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PROCEDURE rw_mem (
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VARIABLE data : INOUT STD_LOGIC_VECTOR;
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VARIABLE data : INOUT STD_LOGIC_VECTOR;
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VARIABLE addr : IN addr_typ;
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VARIABLE addr : IN addr_typ;
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VARIABLE next_cell : INOUT mem_page_ptr;
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VARIABLE next_cell : INOUT mem_page_ptr;
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CONSTANT write_flag : IN BOOLEAN);
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CONSTANT write_flag : IN BOOLEAN);
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PROCEDURE deallocate_mem (
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PROCEDURE deallocate_mem (
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VARIABLE next_cell : INOUT mem_page_ptr);
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VARIABLE next_cell : INOUT mem_page_ptr);
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|
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END PACKAGE linked_list_mem_pkg;
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END PACKAGE linked_list_mem_pkg;
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PACKAGE BODY linked_list_mem_pkg IS
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PACKAGE BODY linked_list_mem_pkg IS
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-- --------------------------------------------------
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-- --------------------------------------------------
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-- The purpose of this procedure is to write a memory location from
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-- The purpose of this procedure is to write a memory location from
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-- the linked list, if the particular page does not exist, create it.
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-- the linked list, if the particular page does not exist, create it.
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-- --------------------------------------------------
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-- --------------------------------------------------
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PROCEDURE rw_mem (
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PROCEDURE rw_mem (
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VARIABLE data : INOUT STD_LOGIC_VECTOR;
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VARIABLE data : INOUT STD_LOGIC_VECTOR;
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VARIABLE addr : IN addr_typ;
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VARIABLE addr : IN addr_typ;
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VARIABLE next_cell : INOUT mem_page_ptr;
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VARIABLE next_cell : INOUT mem_page_ptr;
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CONSTANT write_flag : IN BOOLEAN) IS
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CONSTANT write_flag : IN BOOLEAN) IS
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VARIABLE current_cell_v : mem_page_ptr; -- current page pointer
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VARIABLE current_cell_v : mem_page_ptr; -- current page pointer
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VARIABLE page_address_v : addr_typ; -- calculated page address
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VARIABLE page_address_v : addr_typ; -- calculated page address
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VARIABLE index_v : INTEGER; -- address within the memory page
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VARIABLE index_v : INTEGER; -- address within the memory page
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VARIABLE mem_array_v : mem_array_typ;
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VARIABLE mem_array_v : mem_array_typ;
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BEGIN
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BEGIN
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-- Copy the top of the linked list pointer to a working pointer
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-- Copy the top of the linked list pointer to a working pointer
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current_cell_v := next_cell;
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current_cell_v := next_cell;
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-- Calculate the index within the page from the given address
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-- Calculate the index within the page from the given address
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index_v := addr MOD PAGEDEPTH;
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index_v := addr MOD PAGEDEPTH;
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-- Calculate the page address from the given address
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-- Calculate the page address from the given address
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page_address_v := addr - index_v;
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page_address_v := addr - index_v;
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-- Search through the memory to determine if the calculated
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-- Search through the memory to determine if the calculated
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-- memory page exists. Stop searching when reach the end of
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-- memory page exists. Stop searching when reach the end of
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-- the linked list.
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-- the linked list.
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WHILE ( current_cell_v /= NULL AND
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WHILE ( current_cell_v /= NULL AND
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current_cell_v.page_address /= page_address_v) LOOP
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current_cell_v.page_address /= page_address_v) LOOP
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current_cell_v := current_cell_v.next_cell;
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current_cell_v := current_cell_v.next_cell;
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END LOOP;
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END LOOP;
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IF write_flag THEN
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IF write_flag THEN
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IF ( current_cell_v /= NULL AND -- Check if address exists in memory.
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IF ( current_cell_v /= NULL AND -- Check if address exists in memory.
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current_cell_v.page_address = page_address_v ) THEN
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current_cell_v.page_address = page_address_v ) THEN
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-- Found the memory page the particular address belongs to
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-- Found the memory page the particular address belongs to
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IF ( current_cell_v.mem_array(index_v) /= NULL ) THEN
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IF ( current_cell_v.mem_array(index_v) /= NULL ) THEN
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current_cell_v.mem_array(index_v).ALL := TO_BITVECTOR(data);
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current_cell_v.mem_array(index_v).ALL := TO_BITVECTOR(data);
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ELSE
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ELSE
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current_cell_v.mem_array(index_v) := NEW BIT_VECTOR'(TO_BITVECTOR(data));
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current_cell_v.mem_array(index_v) := NEW BIT_VECTOR'(TO_BITVECTOR(data));
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END IF;
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END IF;
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ELSE
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ELSE
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-- The memory page the address belongs to was not allocated in memory.
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-- The memory page the address belongs to was not allocated in memory.
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-- Allocate page here and assign data.
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-- Allocate page here and assign data.
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mem_array_v(index_v) := NEW BIT_VECTOR'(TO_BITVECTOR(data));
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mem_array_v(index_v) := NEW BIT_VECTOR'(TO_BITVECTOR(data));
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next_cell := NEW mem_page_typ'( mem_array => mem_array_v,
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next_cell := NEW mem_page_typ'( mem_array => mem_array_v,
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page_address => page_address_v,
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page_address => page_address_v,
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next_cell => next_cell);
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next_cell => next_cell);
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END IF;
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END IF;
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ELSE -- Read memory
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ELSE -- Read memory
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IF ( current_cell_v /= NULL AND -- Check if address exists in memory.
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IF ( current_cell_v /= NULL AND -- Check if address exists in memory.
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current_cell_v.page_address = page_address_v AND
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current_cell_v.page_address = page_address_v AND
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current_cell_v.mem_array(index_v) /= NULL ) THEN
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current_cell_v.mem_array(index_v) /= NULL ) THEN
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-- Found the memory page the particular address belongs to,
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-- Found the memory page the particular address belongs to,
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-- and the memory location has valid data.
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-- and the memory location has valid data.
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data := TO_STDLOGICVECTOR(current_cell_v.mem_array(index_v).ALL);
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data := TO_STDLOGICVECTOR(current_cell_v.mem_array(index_v).ALL);
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ELSE
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ELSE
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-- Trying to read from unwritten or unallocated
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-- Trying to read from unwritten or unallocated
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-- memory location, return 'U';
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-- memory location, return 'U';
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data := (data'RANGE => 'U');
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data := (data'RANGE => 'U');
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCEDURE rw_mem;
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END PROCEDURE rw_mem;
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|
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PROCEDURE deallocate_mem (
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PROCEDURE deallocate_mem (
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VARIABLE next_cell : INOUT mem_page_ptr) IS
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VARIABLE next_cell : INOUT mem_page_ptr) IS
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VARIABLE delete_cell_v : mem_page_ptr;
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VARIABLE delete_cell_v : mem_page_ptr;
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BEGIN
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BEGIN
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-- Deallocate the linked link memory from work station memory.
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-- Deallocate the linked link memory from work station memory.
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WHILE next_cell /= NULL LOOP -- while not reached the end of the LL
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WHILE next_cell /= NULL LOOP -- while not reached the end of the LL
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delete_cell_v := next_cell; -- Copy pointer to record for deleting
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delete_cell_v := next_cell; -- Copy pointer to record for deleting
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FOR i IN 0 TO PAGEDEPTH-1 LOOP
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FOR i IN 0 TO PAGEDEPTH-1 LOOP
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IF delete_cell_v.mem_array(i) /= NULL THEN
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IF delete_cell_v.mem_array(i) /= NULL THEN
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deallocate(delete_cell_v.mem_array(i));
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deallocate(delete_cell_v.mem_array(i));
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END IF;
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END IF;
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END LOOP;
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END LOOP;
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next_cell := next_cell.next_cell; -- set pointer to next cell in LL
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next_cell := next_cell.next_cell; -- set pointer to next cell in LL
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deallocate(delete_cell_v); -- Deallocate current cell from memory.
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deallocate(delete_cell_v); -- Deallocate current cell from memory.
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END LOOP;
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END LOOP;
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END PROCEDURE deallocate_mem;
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END PROCEDURE deallocate_mem;
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END PACKAGE BODY linked_list_mem_pkg;
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END PACKAGE BODY linked_list_mem_pkg;
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|
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