----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Single port asynchronous RAM simulation model ----
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---- Single port asynchronous RAM simulation model ----
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---- ----
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---- ----
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---- This file is part of the single_port project ----
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---- This file is part of the single_port project ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- This is a single port asynchronous memory. This files ----
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---- This is a single port asynchronous memory. This files ----
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---- describes three architectures. Two architectures are ----
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---- describes three architectures. Two architectures are ----
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---- traditional array based memories. One describes the memory ----
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---- traditional array based memories. One describes the memory ----
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---- as an array of STD_LOGIC_VECTOR, and the other describes ----
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---- as an array of STD_LOGIC_VECTOR, and the other describes ----
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---- the ARRAY as BIT_VECTOR. ----
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---- the ARRAY as BIT_VECTOR. ----
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---- The third architecture describes the memory arranged as a ----
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---- The third architecture describes the memory arranged as a ----
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---- linked list in order to conserve computer memory usage. The ----
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---- linked list in order to conserve computer memory usage. The ----
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---- memory is organized as a linked list of BIT_VECTOR arrays ----
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---- memory is organized as a linked list of BIT_VECTOR arrays ----
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---- whose size is defined by the constant PAGEDEPTH in ----
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---- whose size is defined by the constant PAGEDEPTH in ----
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---- single_port_pkg.vhd. ----
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---- single_port_pkg.vhd. ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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---- - Robert Paley, rpaley_yid@yahoo.com ----
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---- - Robert Paley, rpaley_yid@yahoo.com ----
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---- - Michael Geng, vhdl@MichaelGeng.de ----
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---- - Michael Geng, vhdl@MichaelGeng.de ----
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---- ----
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---- ----
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---- References: ----
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---- References: ----
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---- 1. The Designer's Guide to VHDL by Peter Ashenden ----
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---- 1. The Designer's Guide to VHDL by Peter Ashenden ----
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---- ISBN: 1-55860-270-4 (pbk.) ----
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---- ISBN: 1-55860-270-4 (pbk.) ----
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---- 2. Writing Testbenches - Functional Verification of HDL ----
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---- 2. Writing Testbenches - Functional Verification of HDL ----
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---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
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---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2005 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2005 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
|
---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
|
---- the original copyright notice and the associated disclaimer. ----
|
---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
|
---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
|
---- either version 2.1 of the License, or (at your option) any ----
|
---- either version 2.1 of the License, or (at your option) any ----
|
---- later version. ----
|
---- later version. ----
|
---- ----
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---- ----
|
---- This source is distributed in the hope that it will be ----
|
---- This source is distributed in the hope that it will be ----
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
---- details. ----
|
---- details. ----
|
---- ----
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---- ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- Public License along with this source; if not, download it ----
|
---- Public License along with this source; if not, download it ----
|
---- from http://www.opencores.org/lgpl.shtml ----
|
---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
|
-- CVS Revision History
|
--
|
--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
|
-- Revision 1.4 2005/11/19 15:18:54 mgeng
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-- Revision 1.4 2005/11/19 15:18:54 mgeng
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-- rnw replaced by nce, nwe and noe, tristate drivers added
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-- rnw replaced by nce, nwe and noe, tristate drivers added
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--
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--
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-- Revision 1.3 2005/10/25 18:26:52 mgeng
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-- Revision 1.3 2005/10/25 18:26:52 mgeng
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-- PAGENUM constant removed because the address bus width provides this information
|
-- PAGENUM constant removed because the address bus width provides this information
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--
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--
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-- Revision 1.2 2005/10/12 19:39:27 mgeng
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-- Revision 1.2 2005/10/12 19:39:27 mgeng
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-- Buses unconstrained, LGPL header added
|
-- Buses unconstrained, LGPL header added
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--
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--
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-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
|
-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
|
-- initial checkin
|
-- initial checkin
|
--
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--
|
-- Revision 1.1 2003/01/14 17:48:31 Default
|
-- Revision 1.1 2003/01/14 17:48:31 Default
|
-- Initial revision
|
-- Initial revision
|
--
|
--
|
-- Revision 1.1 2002/12/24 18:09:05 Default
|
-- Revision 1.1 2002/12/24 18:09:05 Default
|
-- Initial revision
|
-- Initial revision
|
--
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--
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LIBRARY IEEE;
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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USE WORK.single_port_pkg.ALL;
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USE WORK.single_port_pkg.ALL;
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USE WORK.linked_list_mem_pkg.ALL;
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USE WORK.linked_list_mem_pkg.ALL;
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|
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ENTITY single_port IS
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ENTITY single_port IS
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GENERIC (
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GENERIC (
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rnwtQ : TIME := 1 NS);
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rnwtQ : TIME := 1 NS);
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PORT (
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PORT (
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d : IN STD_LOGIC_VECTOR; -- data bus input
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d : IN STD_LOGIC_VECTOR; -- data bus input
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q : OUT STD_LOGIC_VECTOR; -- data bus output
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q : OUT STD_LOGIC_VECTOR; -- data bus output
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a : IN STD_LOGIC_VECTOR; -- address bus
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a : IN STD_LOGIC_VECTOR; -- address bus
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nce : IN STD_LOGIC; -- not chip enable
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nce : IN STD_LOGIC; -- not chip enable
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nwe : IN STD_LOGIC; -- not write enable
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nwe : IN STD_LOGIC; -- not write enable
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noe : IN STD_LOGIC; -- not output enable
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noe : IN STD_LOGIC; -- not output enable
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dealloc_mem : IN BOOLEAN := FALSE); -- control signal for deallocating memory,
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dealloc_mem : IN BOOLEAN := FALSE); -- control signal for deallocating memory,
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-- only used in the linked list implementation
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-- only used in the linked list implementation
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END ENTITY single_port;
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END ENTITY single_port;
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|
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ARCHITECTURE ArrayMemNoFlag OF single_port IS
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ARCHITECTURE ArrayMemNoFlag OF single_port IS
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BEGIN
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BEGIN
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|
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mem_proc : PROCESS(d, a, nce, nwe, noe)
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mem_proc : PROCESS(d, a, nce, nwe, noe)
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TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF STD_LOGIC_VECTOR(d'RANGE);
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TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF STD_LOGIC_VECTOR(d'RANGE);
|
VARIABLE mem : mem_typ;
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VARIABLE mem : mem_typ;
|
BEGIN
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BEGIN
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IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write
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IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write
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mem(TO_INTEGER(unsigned(a))) := d;
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mem(TO_INTEGER(unsigned(a))) := d;
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END IF;
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END IF;
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|
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IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read
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IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read
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q <= mem(TO_INTEGER(unsigned(a))) AFTER rnwtQ;
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q <= mem(TO_INTEGER(unsigned(a))) AFTER rnwtQ;
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ELSE
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ELSE
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q <= (q'RANGE => 'Z') AFTER rnwtQ;
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q <= (q'RANGE => 'Z') AFTER rnwtQ;
|
END IF;
|
END IF;
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END PROCESS mem_proc;
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END PROCESS mem_proc;
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|
|
END ArrayMemNoFlag;
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END ArrayMemNoFlag;
|
|
|
ARCHITECTURE ArrayMem OF single_port IS
|
ARCHITECTURE ArrayMem OF single_port IS
|
BEGIN
|
BEGIN
|
|
|
mem_proc : PROCESS(d, a, nce, nwe, noe)
|
mem_proc : PROCESS(d, a, nce, nwe, noe)
|
TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BIT_VECTOR(d'RANGE);
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TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BIT_VECTOR(d'RANGE);
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TYPE flag_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BOOLEAN;
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TYPE flag_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BOOLEAN;
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VARIABLE mem : mem_typ;
|
VARIABLE mem : mem_typ;
|
VARIABLE flag : flag_typ;
|
VARIABLE flag : flag_typ;
|
BEGIN
|
BEGIN
|
IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write
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IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write
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mem( TO_INTEGER(unsigned(a))) := TO_BITVECTOR(d);
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mem( TO_INTEGER(unsigned(a))) := TO_BITVECTOR(d);
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flag(TO_INTEGER(unsigned(a))) := true; -- set valid memory location flag
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flag(TO_INTEGER(unsigned(a))) := true; -- set valid memory location flag
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END IF;
|
END IF;
|
|
|
IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read
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IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read
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IF ( flag(TO_INTEGER(unsigned(a))) = true ) THEN -- read data, either valid or 'U'
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IF ( flag(TO_INTEGER(unsigned(a))) = true ) THEN -- read data, either valid or 'U'
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q <= TO_STDLOGICVECTOR(mem(TO_INTEGER(unsigned(a)))) AFTER rnwtQ;
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q <= TO_STDLOGICVECTOR(mem(TO_INTEGER(unsigned(a)))) AFTER rnwtQ;
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ELSE -- reading invalid memory location
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ELSE -- reading invalid memory location
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q <= (q'RANGE => 'U') AFTER rnwtQ;
|
q <= (q'RANGE => 'U') AFTER rnwtQ;
|
END IF;
|
END IF;
|
ELSE
|
ELSE
|
q <= (q'RANGE => 'Z') AFTER rnwtQ;
|
q <= (q'RANGE => 'Z') AFTER rnwtQ;
|
END IF;
|
END IF;
|
END PROCESS mem_proc;
|
END PROCESS mem_proc;
|
END ArrayMem;
|
END ArrayMem;
|
|
|
ARCHITECTURE LinkedList OF single_port IS
|
ARCHITECTURE LinkedList OF single_port IS
|
CONSTANT WRITE_MEM : BOOLEAN := true;
|
CONSTANT WRITE_MEM : BOOLEAN := true;
|
CONSTANT READ_MEM : BOOLEAN := false;
|
CONSTANT READ_MEM : BOOLEAN := false;
|
BEGIN
|
BEGIN
|
|
|
mem_proc : PROCESS(d, a, nce, nwe, noe, dealloc_mem)
|
mem_proc : PROCESS(d, a, nce, nwe, noe, dealloc_mem)
|
VARIABLE mem_page_v : mem_page_ptr;
|
VARIABLE mem_page_v : mem_page_ptr;
|
VARIABLE d_v : STD_LOGIC_VECTOR(d'RANGE);
|
VARIABLE d_v : STD_LOGIC_VECTOR(d'RANGE);
|
VARIABLE a_v : addr_typ;
|
VARIABLE a_v : addr_typ;
|
BEGIN
|
BEGIN
|
IF NOT dealloc_mem THEN
|
IF NOT dealloc_mem THEN
|
d_v := d;
|
d_v := d;
|
if (nce = '0') then
|
if (nce = '0') then
|
a_v := TO_INTEGER(unsigned(a));
|
a_v := TO_INTEGER(unsigned(a));
|
end if;
|
end if;
|
IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write
|
IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write
|
rw_mem( data => d_v,
|
rw_mem( data => d_v,
|
addr => a_v,
|
addr => a_v,
|
next_cell => mem_page_v,
|
next_cell => mem_page_v,
|
write_flag => WRITE_MEM);
|
write_flag => WRITE_MEM);
|
END IF;
|
END IF;
|
|
|
IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read
|
IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read
|
rw_mem( data => d_v,
|
rw_mem( data => d_v,
|
addr => a_v,
|
addr => a_v,
|
next_cell => mem_page_v,
|
next_cell => mem_page_v,
|
write_flag => READ_MEM);
|
write_flag => READ_MEM);
|
q <= d_v AFTER rnwtQ;
|
q <= d_v AFTER rnwtQ;
|
ELSE
|
ELSE
|
q <= (q'RANGE => 'Z') AFTER rnwtQ;
|
q <= (q'RANGE => 'Z') AFTER rnwtQ;
|
END IF;
|
END IF;
|
ELSE -- Deallocate memory from work station memory.
|
ELSE -- Deallocate memory from work station memory.
|
deallocate_mem(mem_page_v);
|
deallocate_mem(mem_page_v);
|
END IF;
|
END IF;
|
END PROCESS mem_proc;
|
END PROCESS mem_proc;
|
END LinkedList;
|
END LinkedList;
|
|
|