SOCM_CORE
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SOCM_CORE
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name: adv_debug_sys
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name: Advanced Debug System
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description: Advanced Debug System
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description: Advanced Debug System
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version: ads_3
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id: adv_debug_sys,ads_3
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license: LGPL
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license: LGPL
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licensefile:
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licensefile:
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author:
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author:
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authormail:
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authormail:
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vccmd: svn co http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/tags/ADS_RELEASE_3_0_0/Hardware/adv_dbg_if/rtl rtl
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vccmd: svn co http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/tags/ADS_RELEASE_3_0_0/Hardware/adv_dbg_if/rtl rtl
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toplevel: adbg_top
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toplevel: adbg_top
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interfaces:
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interfaces:
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:jtag: SOCM_IFC
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:jtag: SOCM_IFC
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name: jtag_tap
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name: jtag_tap
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dir: 1
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dir: 1
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version: "1"
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id: jtag_tap,1
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ports:
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ports:
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:tck_i: SOCM_PORT
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:tck_i: SOCM_PORT
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len: 1
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len: 1
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defn: tck
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defn: tck
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:tdi_i: SOCM_PORT
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:tdi_i: SOCM_PORT
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len: 1
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len: 1
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defn: tdi
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defn: tdi
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:tdo_o: SOCM_PORT
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:tdo_o: SOCM_PORT
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len: 1
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len: 1
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defn: tdo
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defn: tdo
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:rst_i: SOCM_PORT
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:rst_i: SOCM_PORT
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len: 1
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len: 1
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defn: rst
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defn: rst
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:shift_dr_i: SOCM_PORT
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:shift_dr_i: SOCM_PORT
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len: 1
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len: 1
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defn: shift
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defn: shift
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:pause_dr_i: SOCM_PORT
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:pause_dr_i: SOCM_PORT
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len: 1
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len: 1
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defn: pause
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defn: pause
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:update_dr_i: SOCM_PORT
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:update_dr_i: SOCM_PORT
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len: 1
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len: 1
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defn: update
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defn: update
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:capture_dr_i: SOCM_PORT
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:capture_dr_i: SOCM_PORT
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len: 1
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len: 1
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defn: capture
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defn: capture
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:debug_select_i: SOCM_PORT
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:debug_select_i: SOCM_PORT
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len: 1
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len: 1
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defn: select
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defn: select
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:wb_ifc: SOCM_IFC
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:wb_ifc: SOCM_IFC
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name: wishbone_ma
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name: wishbone_ma
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dir: 1
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dir: 1
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version: "b3"
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id: wishbone_ma,b3
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ports:
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ports:
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:wb_clk_i: SOCM_PORT
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:wb_clk_i: SOCM_PORT
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len: 1
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len: 1
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defn: clk
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defn: clk
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:wb_rst_i: SOCM_PORT
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:wb_rst_i: SOCM_PORT
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len: 1
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len: 1
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defn: rst
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defn: rst
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:wb_adr_o: SOCM_PORT
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:wb_adr_o: SOCM_PORT
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defn: adr
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defn: adr
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len: 32
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len: 32
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:wb_dat_o: SOCM_PORT
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:wb_dat_o: SOCM_PORT
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defn: dat_i
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defn: dat_i
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len: 32
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len: 32
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:wb_dat_i: SOCM_PORT
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:wb_dat_i: SOCM_PORT
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defn: dat_o
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defn: dat_o
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len: 32
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len: 32
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:wb_cyc_o: SOCM_PORT
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:wb_cyc_o: SOCM_PORT
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defn: cyc
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defn: cyc
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len: 1
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len: 1
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:wb_stb_o: SOCM_PORT
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:wb_stb_o: SOCM_PORT
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defn: stb
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defn: stb
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len: 1
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len: 1
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:wb_sel_o: SOCM_PORT
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:wb_sel_o: SOCM_PORT
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defn: sel
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defn: sel
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len: 4
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len: 4
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:wb_we_o: SOCM_PORT
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:wb_we_o: SOCM_PORT
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defn: we
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defn: we
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len: 1
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len: 1
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:wb_ack_i: SOCM_PORT
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:wb_ack_i: SOCM_PORT
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defn: ack
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defn: ack
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len: 1
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len: 1
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:wb_cab_o: SOCM_PORT
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:wb_cab_o: SOCM_PORT
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defn: cab
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defn: cab
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len: 1
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len: 1
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:wb_err_i: SOCM_PORT
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:wb_err_i: SOCM_PORT
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defn: err
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defn: err
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len: 1
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len: 1
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:wb_cti_o: SOCM_PORT
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:wb_cti_o: SOCM_PORT
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defn: cti
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defn: cti
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len: 3
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len: 3
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:wb_bte_o: SOCM_PORT
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:wb_bte_o: SOCM_PORT
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defn: bte
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defn: bte
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len: 2
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len: 2
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:cpu0_dbg_clk: SOCM_IFC
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:cpu0_dbg_clk: SOCM_IFC
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name: clk
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name: clk
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dir: 1
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dir: 1
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version: "1"
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id: clk,1
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ports:
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ports:
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:cpu0_clk_i: SOCM_PORT
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:cpu0_clk_i: SOCM_PORT
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len: 1
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len: 1
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defn: clk
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defn: clk
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:cpu0_dbg_rst: SOCM_IFC
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:cpu0_dbg_rst: SOCM_IFC
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name: rst
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name: rst
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dir: 0
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dir: 0
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version: "1"
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id: rst,1
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ports:
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ports:
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:cpu0_rst_o: SOCM_PORT
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:cpu0_rst_o: SOCM_PORT
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len: 1
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len: 1
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defn: rst
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defn: rst
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:cpu0_dbg: SOCM_IFC
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:cpu0_dbg: SOCM_IFC
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name: debug
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name: debug
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dir: 0
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dir: 0
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version: "1"
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id: debug,1
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ports:
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ports:
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:cpu0_addr_o: SOCM_PORT
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:cpu0_addr_o: SOCM_PORT
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len: 32
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len: 32
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defn: dbg_adr
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defn: dbg_adr
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:cpu0_data_o: SOCM_PORT
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:cpu0_data_o: SOCM_PORT
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len: 32
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len: 32
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defn: dbg_dat_o
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defn: dbg_dat_o
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:cpu0_data_i: SOCM_PORT
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:cpu0_data_i: SOCM_PORT
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len: 32
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len: 32
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defn: dbg_dat_i
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defn: dbg_dat_i
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:cpu0_bp_i: SOCM_PORT
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:cpu0_bp_i: SOCM_PORT
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len: 1
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len: 1
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defn: dbg_bpo
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defn: dbg_bpo
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:cpu0_stall_o: SOCM_PORT
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:cpu0_stall_o: SOCM_PORT
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defn: dbg_stall
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defn: dbg_stall
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len: 1
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len: 1
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:cpu0_stb_o: SOCM_PORT
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:cpu0_stb_o: SOCM_PORT
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len: 1
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len: 1
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defn: dbg_stb
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defn: dbg_stb
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:cpu0_we_o: SOCM_PORT
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:cpu0_we_o: SOCM_PORT
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len: 1
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len: 1
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defn: dbg_we
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defn: dbg_we
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:cpu0_ack_i: SOCM_PORT
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:cpu0_ack_i: SOCM_PORT
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len: 1
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len: 1
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defn: dbg_ack
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defn: dbg_ack
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# :dbg_ewt_i: SOCM_PORT
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# :dbg_ewt_i: SOCM_PORT
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# len: 1
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# len: 1
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# defn: dbg_ewt
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# defn: dbg_ewt
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# :dbg_lss_o: SOCM_PORT
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# :dbg_lss_o: SOCM_PORT
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# len: 4
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# len: 4
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# defn: dbg_lss
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# defn: dbg_lss
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# :dbg_is_o: SOCM_PORT
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# :dbg_is_o: SOCM_PORT
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# len: 2
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# len: 2
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# defn: dbg_iso
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# defn: dbg_iso
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# :dbg_wp_o: SOCM_PORT
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# :dbg_wp_o: SOCM_PORT
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# len: 11
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# len: 11
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# defn: dbg_wpo
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# defn: dbg_wpo
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hdlfiles:
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hdlfiles:
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:adbg_top: SOCM_HDL_FILE
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:adbg_top: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/adbg_top.v
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path: rtl/verilog/adbg_top.v
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:adbg_crc32: SOCM_HDL_FILE
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:adbg_crc32: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/adbg_crc32.v
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path: rtl/verilog/adbg_crc32.v
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:adbg_defines: SOCM_HDL_FILE
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:adbg_defines: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/adbg_defines.v
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path: rtl/verilog/adbg_defines.v
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:adbg_jsp_biu: SOCM_HDL_FILE
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:adbg_jsp_biu: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/adbg_jsp_biu.v
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path: rtl/verilog/adbg_jsp_biu.v
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:adbg_jsp_module: SOCM_HDL_FILE
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:adbg_jsp_module: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/adbg_jsp_module.v
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path: rtl/verilog/adbg_jsp_module.v
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:adbg_or1k_biu: SOCM_HDL_FILE
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:adbg_or1k_biu: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/adbg_or1k_biu.v
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path: rtl/verilog/adbg_or1k_biu.v
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:adbg_or1k_defines: SOCM_HDL_FILE
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:adbg_or1k_defines: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/adbg_or1k_defines.v
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path: rtl/verilog/adbg_or1k_defines.v
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:adbg_or1k_module: SOCM_HDL_FILE
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:adbg_or1k_module: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/adbg_or1k_module.v
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path: rtl/verilog/adbg_or1k_module.v
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:adbg_or1k_status_reg: SOCM_HDL_FILE
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:adbg_or1k_status_reg: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/adbg_or1k_status_reg.v
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path: rtl/verilog/adbg_or1k_status_reg.v
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:adbg_top: SOCM_HDL_FILE
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:adbg_top: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/adbg_top.v
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path: rtl/verilog/adbg_top.v
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:adbg_wb_biu: SOCM_HDL_FILE
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:adbg_wb_biu: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/adbg_wb_biu.v
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path: rtl/verilog/adbg_wb_biu.v
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:adbg_wb_defines: SOCM_HDL_FILE
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:adbg_wb_defines: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/adbg_wb_defines.v
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path: rtl/verilog/adbg_wb_defines.v
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:adbg_wb_module: SOCM_HDL_FILE
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:adbg_wb_module: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/adbg_wb_module.v
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path: rtl/verilog/adbg_wb_module.v
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:bytefifo: SOCM_HDL_FILE
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:bytefifo: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/bytefifo.v
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path: rtl/verilog/bytefifo.v
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:syncflow: SOCM_HDL_FILE
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:syncflow: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/syncflop.v
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path: rtl/verilog/syncflop.v
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:syncreg: SOCM_HDL_FILE
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:syncreg: SOCM_HDL_FILE
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use_syn: true
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use_syn: true
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use_sim: true
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use_sim: true
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type: verilog
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type: verilog
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path: rtl/verilog/syncreg.v
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path: rtl/verilog/syncreg.v
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