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[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [or1200_rel2/] [01_or1200.yaml] - Diff between revs 7 and 10

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Rev 7	Rev 10
`SOCM_CORE`	`SOCM_CORE`
`name: or1200`	`name: OpenRISC 1200`
`description: OpenRISC CPU`	`description: OpenRISC CPU`
`version: rel2`	`id: or1200,rel2`
`license: LGPL`	`license: LGPL`
`licensefile:`	`licensefile:`
`author:`	`author:`
`authormail:`	`authormail:`
`vccmd: svn co http://opencores.org/ocsvn/openrisc/openrisc/tags/or1200/rel2/rtl rtl`	`vccmd: svn co http://opencores.org/ocsvn/openrisc/openrisc/tags/or1200/rel2/rtl rtl`
`toplevel: or1200_top`	`toplevel: or1200_top`
`interfaces:`	`interfaces:`
`:clmode: SOCM_IFC`	`:clmode: SOCM_IFC`
`name: single`	`name: single`
`dir: 1`	`dir: 1`
`version: "1"`	`id: single,1`
`ports:`	`ports:`
`:clmode_i: SOCM_PORT`	`:clmode_i: SOCM_PORT`
`len: 2`	`len: 2`
`defn: single`	`defn: single`

`:pic_ints: SOCM_IFC`	`:pic_ints: SOCM_IFC`
`name: single`	`name: single`
`dir: 1`	`dir: 1`
`version: "1"`	`id: single,1`
`ports:`	`ports:`
`:pic_ints_i: SOCM_PORT`	`:pic_ints_i: SOCM_PORT`
`len: 20`	`len: 20`
`defn: single`	`defn: single`

`:clk: SOCM_IFC`	`:clk: SOCM_IFC`
`name: clk`	`name: clk`
`dir: 1`	`dir: 1`
`version: "1"`	`id: clk,1`
`ports:`	`ports:`
`:clk_i: SOCM_PORT`	`:clk_i: SOCM_PORT`
`len: 1`	`len: 1`
`defn: clk`	`defn: clk`

`:rst: SOCM_IFC`	`:rst: SOCM_IFC`
`name: rst`	`name: rst`
`dir: 1`	`dir: 1`
`version: "1"`	`id: rst,1`
`ports:`	`ports:`
`:rst_i: SOCM_PORT`	`:rst_i: SOCM_PORT`
`len: 1`	`len: 1`
`defn: rst`	`defn: rst`

`:wb_instruction: SOCM_IFC`	`:wb_instruction: SOCM_IFC`
`name: wishbone_ma`	`name: wishbone_ma`
`dir: 1`	`dir: 1`
`version: "b3"`	`id: wishbone_ma,b3`
`ports:`	`ports:`
`:iwb_clk_i: SOCM_PORT`	`:iwb_clk_i: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:iwb_rst_i: SOCM_PORT`	`:iwb_rst_i: SOCM_PORT`
`defn: rst`	`defn: rst`
`len: 1`	`len: 1`
`:iwb_cyc_o: SOCM_PORT`	`:iwb_cyc_o: SOCM_PORT`
`defn: cyc`	`defn: cyc`
`len: 1`	`len: 1`
`:iwb_stb_o: SOCM_PORT`	`:iwb_stb_o: SOCM_PORT`
`defn: stb`	`defn: stb`
`len: 1`	`len: 1`
`:iwb_adr_o: SOCM_PORT`	`:iwb_adr_o: SOCM_PORT`
`defn: adr`	`defn: adr`
`len: 32`	`len: 32`
`:iwb_sel_o: SOCM_PORT`	`:iwb_sel_o: SOCM_PORT`
`defn: sel`	`defn: sel`
`len: 4`	`len: 4`
`:iwb_we_o: SOCM_PORT`	`:iwb_we_o: SOCM_PORT`
`defn: we`	`defn: we`
`len: 1`	`len: 1`
`:iwb_dat_o: SOCM_PORT`	`:iwb_dat_o: SOCM_PORT`
`defn: dat_i`	`defn: dat_i`
`len: 32`	`len: 32`
`:iwb_dat_i: SOCM_PORT`	`:iwb_dat_i: SOCM_PORT`
`defn: dat_o`	`defn: dat_o`
`len: 32`	`len: 32`
`:iwb_ack_i: SOCM_PORT`	`:iwb_ack_i: SOCM_PORT`
`defn: ack`	`defn: ack`
`len: 1`	`len: 1`
`:iwb_err_i: SOCM_PORT`	`:iwb_err_i: SOCM_PORT`
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:iwb_rty_i: SOCM_PORT`	`:iwb_rty_i: SOCM_PORT`
`defn: rty`	`defn: rty`
`len: 1`	`len: 1`

`:wb_data: SOCM_IFC`	`:wb_data: SOCM_IFC`
`name: wishbone_ma`	`name: wishbone_ma`
`dir: 1`	`dir: 1`
`version: "b3"`	`id: wishbone_ma,b3`
`ports:`	`ports:`
`:dwb_clk_i: SOCM_PORT`	`:dwb_clk_i: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:dwb_rst_i: SOCM_PORT`	`:dwb_rst_i: SOCM_PORT`
`defn: rst`	`defn: rst`
`len: 1`	`len: 1`
`:dwb_cyc_o: SOCM_PORT`	`:dwb_cyc_o: SOCM_PORT`
`defn: cyc`	`defn: cyc`
`len: 1`	`len: 1`
`:dwb_stb_o: SOCM_PORT`	`:dwb_stb_o: SOCM_PORT`
`defn: stb`	`defn: stb`
`len: 1`	`len: 1`
`:dwb_adr_o: SOCM_PORT`	`:dwb_adr_o: SOCM_PORT`
`defn: adr`	`defn: adr`
`len: 32`	`len: 32`
`:dwb_sel_o: SOCM_PORT`	`:dwb_sel_o: SOCM_PORT`
`defn: sel`	`defn: sel`
`len: 4`	`len: 4`
`:dwb_we_o: SOCM_PORT`	`:dwb_we_o: SOCM_PORT`
`defn: we`	`defn: we`
`len: 1`	`len: 1`
`:dwb_dat_o: SOCM_PORT`	`:dwb_dat_o: SOCM_PORT`
`defn: dat_i`	`defn: dat_i`
`len: 32`	`len: 32`
`:dwb_dat_i: SOCM_PORT`	`:dwb_dat_i: SOCM_PORT`
`defn: dat_o`	`defn: dat_o`
`len: 32`	`len: 32`
`:dwb_ack_i: SOCM_PORT`	`:dwb_ack_i: SOCM_PORT`
`defn: ack`	`defn: ack`
`len: 1`	`len: 1`
`:dwb_err_i: SOCM_PORT`	`:dwb_err_i: SOCM_PORT`
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:dwb_rty_i: SOCM_PORT`	`:dwb_rty_i: SOCM_PORT`
`defn: rty`	`defn: rty`
`len: 1`	`len: 1`

`:ext_debug: SOCM_IFC`	`:ext_debug: SOCM_IFC`
`name: debug`	`name: debug`
`dir: 1`	`dir: 1`
`version: "1"`	`id: debug,1`
`ports:`	`ports:`
`:dbg_stall_i: SOCM_PORT`	`:dbg_stall_i: SOCM_PORT`
`defn: dbg_stall`	`defn: dbg_stall`
`len: 1`	`len: 1`
`:dbg_ewt_i: SOCM_PORT`	`:dbg_ewt_i: SOCM_PORT`
`len: 1`	`len: 1`
`defn: dbg_ewt`	`defn: dbg_ewt`
`:dbg_lss_o: SOCM_PORT`	`:dbg_lss_o: SOCM_PORT`
`len: 4`	`len: 4`
`defn: dbg_lss`	`defn: dbg_lss`
`:dbg_is_o: SOCM_PORT`	`:dbg_is_o: SOCM_PORT`
`len: 2`	`len: 2`
`defn: dbg_iso`	`defn: dbg_iso`
`:dbg_wp_o: SOCM_PORT`	`:dbg_wp_o: SOCM_PORT`
`len: 11`	`len: 11`
`defn: dbg_wpo`	`defn: dbg_wpo`
`:dbg_bp_o: SOCM_PORT`	`:dbg_bp_o: SOCM_PORT`
`len: 1`	`len: 1`
`defn: dbg_bpo`	`defn: dbg_bpo`
`:dbg_stb_i: SOCM_PORT`	`:dbg_stb_i: SOCM_PORT`
`len: 1`	`len: 1`
`defn: dbg_stb`	`defn: dbg_stb`
`:dbg_we_i: SOCM_PORT`	`:dbg_we_i: SOCM_PORT`
`len: 1`	`len: 1`
`defn: dbg_we`	`defn: dbg_we`
`:dbg_adr_i: SOCM_PORT`	`:dbg_adr_i: SOCM_PORT`
`len: 32`	`len: 32`
`defn: dbg_adr`	`defn: dbg_adr`
`:dbg_dat_i: SOCM_PORT`	`:dbg_dat_i: SOCM_PORT`
`len: 32`	`len: 32`
`defn: dbg_dat_o`	`defn: dbg_dat_o`
`:dbg_dat_o: SOCM_PORT`	`:dbg_dat_o: SOCM_PORT`
`len: 32`	`len: 32`
`defn: dbg_dat_i`	`defn: dbg_dat_i`
`:dbg_ack_o: SOCM_PORT`	`:dbg_ack_o: SOCM_PORT`
`len: 1`	`len: 1`
`defn: dbg_ack`	`defn: dbg_ack`

`:pow_man: SOCM_IFC`	`:pow_man: SOCM_IFC`
`name: or_power_management`	`name: or_power_management`
`dir: 1`	`dir: 1`
`version: "1"`	`id: or_power_management,1`
`ports:`	`ports:`
`:pm_cpustall_i: SOCM_PORT`	`:pm_cpustall_i: SOCM_PORT`
`len: 1`	`len: 1`
`defn: pm_cpustall`	`defn: pm_cpustall`
`:pm_clksd_o: SOCM_PORT`	`:pm_clksd_o: SOCM_PORT`
`len: 4`	`len: 4`
`defn: pm_clksd`	`defn: pm_clksd`
`:pm_dc_gate_o: SOCM_PORT`	`:pm_dc_gate_o: SOCM_PORT`
`len: 1`	`len: 1`
`defn: pm_dc_gate`	`defn: pm_dc_gate`
`:pm_ic_gate_o: SOCM_PORT`	`:pm_ic_gate_o: SOCM_PORT`
`len: 1`	`len: 1`
`defn: pm_ic_gate`	`defn: pm_ic_gate`
`:pm_dmmu_gate_o: SOCM_PORT`	`:pm_dmmu_gate_o: SOCM_PORT`
`len: 1`	`len: 1`
`defn: pm_dmmu_gate`	`defn: pm_dmmu_gate`
`:pm_immu_gate_o: SOCM_PORT`	`:pm_immu_gate_o: SOCM_PORT`
`len: 1`	`len: 1`
`defn: pm_immu_gate`	`defn: pm_immu_gate`
`:pm_tt_gate_o: SOCM_PORT`	`:pm_tt_gate_o: SOCM_PORT`
`len: 1`	`len: 1`
`defn: pm_tt_gate`	`defn: pm_tt_gate`
`:pm_cpu_gate_o: SOCM_PORT`	`:pm_cpu_gate_o: SOCM_PORT`
`len: 1`	`len: 1`
`defn: pm_cpu_gate`	`defn: pm_cpu_gate`
`:pm_wakeup_o: SOCM_PORT`	`:pm_wakeup_o: SOCM_PORT`
`len: 1`	`len: 1`
`defn: pm_wakeup`	`defn: pm_wakeup`
`:pm_lvolt_o: SOCM_PORT`	`:pm_lvolt_o: SOCM_PORT`
`len: 1`	`len: 1`
`defn: pm_lvolt`	`defn: pm_lvolt`

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[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [or1200_rel2/] [01_or1200.yaml] - Diff between revs 7 and 10