require_relative '../../lib/soc_maker'
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require_relative '../../lib/soc_maker'
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options = {}
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options = {}
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options[ :libpath ] = "./core_lib/"
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options[ :libpath ] = "./core_lib/"
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##
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##
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# initialize SOCMaker core
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# initialize SOCMaker core
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# this sets up logging and parses all yaml files
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# this sets up logging and parses all yaml files
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# found in the configure path (see also soc_maker_conf.rb)
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# found in the configure path (see also soc_maker_conf.rb)
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SOCMaker::load( options )
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SOCMaker::load( options )
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puts "Library Content:"
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puts "Library Content:"
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puts SOCMaker::lib
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puts SOCMaker::lib
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SOCMaker::lib.cores do |name_version, core|
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SOCMaker::lib.cores do |name_version, core|
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# core.get_files
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# core.update_vcs
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end
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end
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soc = SOCMaker::SOCDef.new( 'or1200_test', 'v1', 'or1200_test' )
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soc = SOCMaker::SOCDef.new( 'or1200_test', 'v1', 'or1200_test' )
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SOCMaker::lib.add_core( soc )
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SOCMaker::lib.add_core( soc )
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soc_inst = SOCMaker::CoreInst.new( 'or1200_testv1' )
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soc_inst = SOCMaker::CoreInst.new( 'or1200_testv1' )
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#soc_inst.name = "soc_inst"
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#soc_inst.name = "soc_inst"
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port = SOCMaker::IfcPort.new( 'clk', 1 )
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port = SOCMaker::IfcPort.new( 'clk', 1 )
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ifc = SOCMaker::IfcDef.new( 'clk', '1', 1, { 'clk_i' => port} )
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ifc = SOCMaker::IfcDef.new( 'clk', '1', 1, { 'clk_i' => port} )
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soc.interfaces[ 'clk_ifc'.to_sym ] = ifc
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soc.interfaces[ 'clk_ifc'.to_sym ] = ifc
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port = SOCMaker::IfcPort.new( 'rst', 1 )
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port = SOCMaker::IfcPort.new( 'rst', 1 )
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ifc = SOCMaker::IfcDef.new( 'rst', '1', 1, { 'rst_i' => port} )
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ifc = SOCMaker::IfcDef.new( 'rst', '1', 1, { 'rst_i' => port} )
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soc.interfaces[ 'rst_ifc'.to_sym ] = ifc
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soc.interfaces[ 'rst_ifc'.to_sym ] = ifc
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soc.interfaces[ 'jtag_ifc'.to_sym ] = SOCMaker::IfcDef.new( 'jtag_tap', '1', 1, {
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soc.interfaces[ 'jtag_ifc'.to_sym ] = SOCMaker::IfcDef.new( 'jtag_tap', '1', 1, {
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'tck_i' => SOCMaker::IfcPort.new( 'tck', 1 ),
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'tck_i' => SOCMaker::IfcPort.new( 'tck', 1 ),
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'tdi_i' => SOCMaker::IfcPort.new( 'tdi', 1 ),
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'tdi_i' => SOCMaker::IfcPort.new( 'tdi', 1 ),
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'tdo_o' => SOCMaker::IfcPort.new( 'tdo' ,1 ),
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'tdo_o' => SOCMaker::IfcPort.new( 'tdo' ,1 ),
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'debug_rst_i' => SOCMaker::IfcPort.new( 'rst', 1 ),
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'debug_rst_i' => SOCMaker::IfcPort.new( 'rst', 1 ),
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'shift_dr_i' => SOCMaker::IfcPort.new( 'shift', 1 ),
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'shift_dr_i' => SOCMaker::IfcPort.new( 'shift', 1 ),
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'pause_dr_i' => SOCMaker::IfcPort.new( 'pause', 1 ),
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'pause_dr_i' => SOCMaker::IfcPort.new( 'pause', 1 ),
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'update_dr_i' => SOCMaker::IfcPort.new( 'update', 1 ),
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'update_dr_i' => SOCMaker::IfcPort.new( 'update', 1 ),
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'capture_dr_i' => SOCMaker::IfcPort.new( 'capture', 1 ),
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'capture_dr_i' => SOCMaker::IfcPort.new( 'capture', 1 ),
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'debug_select_i' => SOCMaker::IfcPort.new( 'select', 1 ) } )
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'debug_select_i' => SOCMaker::IfcPort.new( 'select', 1 ) } )
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soc.interfaces[ 'uart_ifc'.to_sym ] = SOCMaker::IfcDef.new( 'uart', '1', 1, {
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soc.interfaces[ 'uart_ifc'.to_sym ] = SOCMaker::IfcDef.new( 'uart', '1', 1, {
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'stx_pad_o' => SOCMaker::IfcPort.new( 'stx_pad', 1 ),
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'stx_pad_o' => SOCMaker::IfcPort.new( 'stx_pad', 1 ),
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'srx_pad_i' => SOCMaker::IfcPort.new( 'srx_pad', 1 ),
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'srx_pad_i' => SOCMaker::IfcPort.new( 'srx_pad', 1 ),
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'rts_pad_o' => SOCMaker::IfcPort.new( 'rts_pad', 1 ),
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'rts_pad_o' => SOCMaker::IfcPort.new( 'rts_pad', 1 ),
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'cts_pad_i' => SOCMaker::IfcPort.new( 'cts_pad', 1 ),
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'cts_pad_i' => SOCMaker::IfcPort.new( 'cts_pad', 1 ),
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'dtr_pad_o' => SOCMaker::IfcPort.new( 'dtr_pad', 1 ),
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'dtr_pad_o' => SOCMaker::IfcPort.new( 'dtr_pad', 1 ),
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'dsr_pad_i' => SOCMaker::IfcPort.new( 'dsr_pad', 1 ),
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'dsr_pad_i' => SOCMaker::IfcPort.new( 'dsr_pad', 1 ),
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'ri_pad_i' => SOCMaker::IfcPort.new( 'ri_pad' , 1 ),
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'ri_pad_i' => SOCMaker::IfcPort.new( 'ri_pad' , 1 ),
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'dcd_pad_i' => SOCMaker::IfcPort.new( 'dcd_pad', 1 ) } )
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'dcd_pad_i' => SOCMaker::IfcPort.new( 'dcd_pad', 1 ) } )
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soc.add_core( 'or1200', 'rel2', 'cpu' )
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soc.add_core( 'or1200', 'rel2', 'cpu' )
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soc.add_core( 'wb_connect', '1', 'wb_bus' )
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soc.add_core( 'wb_connect', '1', 'wb_bus' )
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soc.add_core( 'adv_debug_sys', 'ads_3', 'dbg' )
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soc.add_core( 'adv_debug_sys', 'ads_3', 'dbg' )
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soc.add_core( 'ram_wb', 'b3', 'ram1' )
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soc.add_core( 'ram_wb', 'b3', 'ram1' )
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soc.add_core( 'ram_wb', 'b3', 'ram2' )
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soc.add_core( 'ram_wb', 'b3', 'ram2' )
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soc.add_core( 'uart16550', 'rel4', 'uart' )
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soc.add_core( 'uart16550', 'rel4', 'uart' )
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soc.consistency_check
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soc.consistency_check
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#
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#
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# Setup the CPU
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# Setup the CPU
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#
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#
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soc.set_sparam( 'or1200rel2', 'VCD_DUMP', false )
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soc.set_sparam( 'or1200rel2', 'VCD_DUMP', false )
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soc.set_sparam( 'or1200rel2', 'VERBOSE', false )
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soc.set_sparam( 'or1200rel2', 'VERBOSE', false )
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soc.set_sparam( 'or1200rel2', 'ASIC' , false )
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soc.set_sparam( 'or1200rel2', 'ASIC' , false )
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soc.set_sparam( 'or1200rel2', 'ASIC_MEM_CHOICE', 0 )
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soc.set_sparam( 'or1200rel2', 'ASIC_MEM_CHOICE', 0 )
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soc.set_sparam( 'or1200rel2', 'ASIC_NO_DC', true )
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soc.set_sparam( 'or1200rel2', 'ASIC_NO_DC', true )
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soc.set_sparam( 'or1200rel2', 'ASIC_NO_IC', true )
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soc.set_sparam( 'or1200rel2', 'ASIC_NO_IC', true )
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soc.set_sparam( 'or1200rel2', 'ASIC_NO_DMMU', true )
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soc.set_sparam( 'or1200rel2', 'ASIC_NO_DMMU', true )
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soc.set_sparam( 'or1200rel2', 'ASIC_NO_IMMU', true )
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soc.set_sparam( 'or1200rel2', 'ASIC_NO_IMMU', true )
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soc.set_sparam( 'or1200rel2', 'ASIC_MUL_CHOICE', 0 )
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soc.set_sparam( 'or1200rel2', 'ASIC_MUL_CHOICE', 0 )
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soc.set_sparam( 'or1200rel2', 'ASIC_IC_CHOICE', 0 )
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soc.set_sparam( 'or1200rel2', 'ASIC_IC_CHOICE', 0 )
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soc.set_sparam( 'or1200rel2', 'ASIC_DC_CHOICE', 0 )
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soc.set_sparam( 'or1200rel2', 'ASIC_DC_CHOICE', 0 )
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soc.set_sparam( 'or1200rel2', 'FPGA_MEM_CHOICE', 0 )
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soc.set_sparam( 'or1200rel2', 'FPGA_MEM_CHOICE', 0 )
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soc.set_sparam( 'or1200rel2', 'FPGA_NO_DC', true )
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soc.set_sparam( 'or1200rel2', 'FPGA_NO_DC', true )
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soc.set_sparam( 'or1200rel2', 'FPGA_NO_IC', true )
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soc.set_sparam( 'or1200rel2', 'FPGA_NO_IC', true )
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soc.set_sparam( 'or1200rel2', 'FPGA_NO_DMMU', true )
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soc.set_sparam( 'or1200rel2', 'FPGA_NO_DMMU', true )
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soc.set_sparam( 'or1200rel2', 'FPGA_NO_IMMU', true )
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soc.set_sparam( 'or1200rel2', 'FPGA_NO_IMMU', true )
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soc.set_sparam( 'or1200rel2', 'FPGA_MUL_CHOICE', 1 )
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soc.set_sparam( 'or1200rel2', 'FPGA_MUL_CHOICE', 1 )
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soc.set_sparam( 'or1200rel2', 'FPGA_IC_CHOICE', 0 )
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soc.set_sparam( 'or1200rel2', 'FPGA_IC_CHOICE', 0 )
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soc.set_sparam( 'or1200rel2', 'FPGA_DC_CHOICE', 0 )
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soc.set_sparam( 'or1200rel2', 'FPGA_DC_CHOICE', 0 )
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#
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#
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# Setup the on-chip memory
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# Setup the on-chip memory
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#
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#
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soc.set_sparam( 'ram_wbb3', 'MEM_SIZE', 20 )
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soc.set_sparam( 'ram_wbb3', 'MEM_SIZE', 20 )
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soc.set_sparam( 'ram_wbb3', 'MEM_ADR_WIDTH', 17 )
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soc.set_sparam( 'ram_wbb3', 'MEM_ADR_WIDTH', 17 )
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#
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#
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#
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#
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#
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#
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soc.add_connection( 'or1200_test', 'clk_ifc', 'cpu', 'clk', 'con_main_clk' )
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soc.add_connection( 'or1200_test', 'clk_ifc', 'cpu', 'clk', 'con_main_clk' )
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soc.add_connection( 'or1200_test', 'rst_ifc', 'cpu', 'rst', 'con_main_rst' )
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soc.add_connection( 'or1200_test', 'rst_ifc', 'cpu', 'rst', 'con_main_rst' )
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soc.add_connection( 'or1200_test', 'clk_ifc', 'wb_bus', 'clk', 'con_main_clk' )
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soc.add_connection( 'or1200_test', 'clk_ifc', 'wb_bus', 'clk', 'con_main_clk' )
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soc.add_connection( 'or1200_test', 'rst_ifc', 'wb_bus', 'rst', 'con_main_rst' )
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soc.add_connection( 'or1200_test', 'rst_ifc', 'wb_bus', 'rst', 'con_main_rst' )
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soc.add_connection( 'wb_bus', 'i3', 'dbg', 'wb_ifc', 'con_wb_debug' )
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soc.add_connection( 'wb_bus', 'i3', 'dbg', 'wb_ifc', 'con_wb_debug' )
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soc.add_connection( 'wb_bus', 'i4', 'cpu', 'wb_data', 'con_data' )
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soc.add_connection( 'wb_bus', 'i4', 'cpu', 'wb_data', 'con_data' )
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soc.add_connection( 'wb_bus', 'i5', 'cpu', 'wb_instruction', 'con_instruction' )
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soc.add_connection( 'wb_bus', 'i5', 'cpu', 'wb_instruction', 'con_instruction' )
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soc.add_connection( 'wb_bus', 't0', 'ram1', 'wb_ifc', 'con_ram1' )
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soc.add_connection( 'wb_bus', 't0', 'ram1', 'wb_ifc', 'con_ram1' )
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soc.add_connection( 'wb_bus', 't1', 'ram2', 'wb_ifc', 'con_ram2' )
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soc.add_connection( 'wb_bus', 't1', 'ram2', 'wb_ifc', 'con_ram2' )
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soc.add_connection( 'wb_bus', 't2', 'uart', 'wb_ifc', 'con_uart' )
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soc.add_connection( 'wb_bus', 't2', 'uart', 'wb_ifc', 'con_uart' )
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soc.add_connection( 'dbg', 'cpu0_dbg', 'cpu', 'ext_debug', 'con_debug' )
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soc.add_connection( 'dbg', 'cpu0_dbg', 'cpu', 'ext_debug', 'con_debug' )
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soc.add_connection( 'or1200_test', 'clk_ifc', 'dbg', 'cpu0_dbg_clk', 'con_main_clk' )
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soc.add_connection( 'or1200_test', 'clk_ifc', 'dbg', 'cpu0_dbg_clk', 'con_main_clk' )
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soc.add_connection( 'or1200_test', 'jtag_ifc', 'dbg', 'jtag', 'con_jtag_top' )
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soc.add_connection( 'or1200_test', 'jtag_ifc', 'dbg', 'jtag', 'con_jtag_top' )
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soc.add_connection( 'or1200_test', 'uart_ifc', 'uart', 'uart_ifc', 'con_uart_top' )
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soc.add_connection( 'or1200_test', 'uart_ifc', 'uart', 'uart_ifc', 'con_uart_top' )
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soc_inst.consistency_check
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soc_inst.consistency_check
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soc_inst.gen_toplevel
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soc_inst.gen_toplevel
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soc.copy_files
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soc.copy_files
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