###############################################################
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###############################################################
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#
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#
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# File: conf.rb
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# File: conf.rb
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#
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#
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# Author: Christian Hättich
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# Author: Christian Hättich
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#
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#
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# Project: System-On-Chip Maker
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# Project: System-On-Chip Maker
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#
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#
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# Target: Linux / Windows / Mac
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# Target: Linux / Windows / Mac
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#
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#
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# Language: ruby
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# Language: ruby
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#
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#
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#
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#
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###############################################################
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###############################################################
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#
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#
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#
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#
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# Copyright (C) 2014 Christian Hättich - feddischson [ at ] opencores.org
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# Copyright (C) 2014 Christian Hättich - feddischson [ at ] opencores.org
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#
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#
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# This program is free software: you can redistribute it and/or modify
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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# (at your option) any later version.
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#
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#
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# This program is distributed in the hope that it will be useful,
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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# GNU General Public License for more details.
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#
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#
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# You should have received a copy of the GNU General Public License
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see .
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# along with this program. If not, see .
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#
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#
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#
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#
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###############################################################
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###############################################################
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#
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#
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# Description:
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# Description:
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#
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#
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# This class holds all the configuration and is
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# This class holds all the configuration and is
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# realized as singleton.
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# realized as singleton.
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# The instance can be accessed via Conf::instance
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# The instance can be accessed via Conf::instance
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# The configuration is splitted into two parts:
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# The configuration is splitted into two parts:
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# @data -> user-configurable
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# @data -> user-configurable
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# @data_ro -> read-only
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# @data_ro -> read-only
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#
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#
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#
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#
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#
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#
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######
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######
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#
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#
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# TODO
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# TODO
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# - functionallity to modify @data
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# - functionallity to modify @data
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#
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#
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###############################################################
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###############################################################
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module SOCMaker
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module SOCMaker
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class Conf
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class Conf
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include YAML_EXT
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include YAML_EXT
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include ERR
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include ERR
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private_class_method :new
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private_class_method :new
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def Conf.instance
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def Conf.instance
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@@inst = new if @@inst == nil
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@@inst = new if @@inst == nil
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return @@inst
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return @@inst
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end
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end
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def initialize( optional = {} )
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def initialize( optional = {} )
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init_with( optional.merge( { 'data' => {
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init_with( optional.merge( { 'data' => {
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# the name of this application/tool
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# the name of this application/tool
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:app_name => 'SOC-Maker',
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:app_name => 'SOC-Maker',
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# the name of the tool's commandline interface
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# the name of the tool's commandline interface
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:app_cli_name => 'SOC-Maker CLI',
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:app_cli_name => 'SOC-Maker CLI',
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|
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# array of core search paths
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# array of core search paths
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:cores_search_path => [ './' ],
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:cores_search_path => [ './' ],
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# VHDL include directive
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# VHDL include directive
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:vhdl_include => "library ieee;\nuse ieee.std_logic_1164.ALL;",
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:vhdl_include => "library ieee;\nuse ieee.std_logic_1164.ALL;",
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# build directory, where the whole synthese and build process
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# build directory, where the whole synthese and build process
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# happens
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# happens
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:build_dir => 'build',
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:build_dir => 'build',
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# the folder inside build_dir, where all the vhdl source is placed
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# the folder inside build_dir, where all the vhdl source is placed
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:hdl_dir => 'hdl',
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:hdl_dir => 'hdl',
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# synthesis directory inside build_dir
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# synthesis directory inside build_dir
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:syn_dir => 'syn',
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:syn_dir => 'syn',
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# simulation directory inside build_dir
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# simulation directory inside build_dir
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:sim_dir => 'sim'
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:sim_dir => 'sim'
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} } ) )
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} } ) )
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end
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end
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def encoder_with( coder )
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def encoder_with( coder )
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coder[ 'data' ] = @data
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coder[ 'data' ] = @data
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end
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end
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def init_with( coder )
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def init_with( coder )
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serr_if( coder[ 'data' ] == nil,
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serr_if( coder[ 'data' ] == nil,
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"No configuration data provided",
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"No configuration data provided",
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field: 'data' )
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field: 'data' )
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@data = coder[ 'data' ]
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@data = coder[ 'data' ]
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%w[ app_name vhdl_include
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%w[ app_name vhdl_include
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build_dir hdl_dir
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build_dir hdl_dir
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syn_dir sim_dir ].each do |d|
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syn_dir sim_dir ].each do |d|
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serr_if( @data[ d.to_sym ] == nil,
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serr_if( @data[ d.to_sym ] == nil,
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"Data field '#{d}' is not provided",
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"Data field '#{d}' is not provided",
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field: 'data' )
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field: 'data' )
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verr_if( !@data[ d.to_sym ].is_a?( String ),
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verr_if( !@data[ d.to_sym ].is_a?( String ),
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"Data field '#{d}' is not of type String",
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"Data field '#{d}' is not of type String",
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field: 'data' )
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field: 'data' )
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verr_if( @data[ d.to_sym ].size == 0,
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verr_if( @data[ d.to_sym ].size == 0,
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"Data field '#{d}' is not of type String",
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"Data field '#{d}' is not of type String",
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field: 'data' )
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field: 'data' )
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end
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end
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@data_ro = {
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@data_ro = {
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:yaml_classes => [ SOCMaker::CoreDef,
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:yaml_classes => [ SOCMaker::CoreDef,
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SOCMaker::SOCDef,
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SOCMaker::SOCDef,
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SOCMaker::IfcSpc,
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SOCMaker::IfcSpc,
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SOCMaker::LibInc,
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SOCMaker::LibInc,
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SOCMaker::Conf,
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SOCMaker::Conf,
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SOCMaker::CoreInst ],
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SOCMaker::CoreInst ],
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# Regular expression, which is evaluatted to detect values like
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# Regular expression, which is evaluatted to detect values like
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# eval function_name
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# eval function_name
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# The function_name is used for further processing
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# The function_name is used for further processing
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:eval_regex => /eval +([a-zA-Z_1-9]+)/,
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:eval_regex => /eval +([a-zA-Z_1-9]+)/,
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# Regular expression to check, if it is VHDL or verilog
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# Regular expression to check, if it is VHDL or verilog
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:hdl_type_regex => /(\bvhdl\b)|(\bverilog\b)/,
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:hdl_type_regex => /(\bvhdl\b)|(\bverilog\b)/,
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#
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#
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# Regular expression for vhdl file detection
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# Regular expression for vhdl file detection
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#
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#
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:vhdl_file_regex => /\A\S+\.vhd\Z/,
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:vhdl_file_regex => /\A\S+\.vhd\Z/,
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#
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#
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# Regular expression for verilog file detection
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# Regular expression for verilog file detection
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#
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#
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:verilog_file_regex => /\A\S+\.v\Z/,
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:verilog_file_regex => /\A\S+\.v\Z/,
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#
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#
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# Regular expression to match names starting with non-number
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# Regular expression to match names starting with non-number
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#
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#
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:length_regex => /\A[^0-9]+.*\Z/,
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:length_regex => /\A[^0-9]+.*\Z/,
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#
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#
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# Regular expression to match a component's name (core-name or SOC-name)
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# Regular expression to match a component's name (core-name or SOC-name)
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# (Obsolete)
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#
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#
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:name_regex => /^[a-zA-Z]+[a-zA-Z0-9_\-]*$/,
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:name_regex => /^[a-zA-Z]+[a-zA-Z0-9_\-]*$/,
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:YPP_LUT => {
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:YPP_LUT => {
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/\bSOCM_CONF\b/ => '--- !ruby/object:SOCMaker::Conf',
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/\bSOCM_CONF\b/ => '--- !ruby/object:SOCMaker::Conf',
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/\bSOCM_CORE\b/ => '--- !ruby/object:SOCMaker::CoreDef',
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/\bSOCM_CORE\b/ => '--- !ruby/object:SOCMaker::CoreDef',
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/\bSOCM_SOC\b/ => '--- !ruby/object:SOCMaker::SOCDef',
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/\bSOCM_SOC\b/ => '--- !ruby/object:SOCMaker::SOCDef',
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/\bSOCM_IFC_SPC\b/ => '--- !ruby/object:SOCMaker::IfcSpc',
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/\bSOCM_IFC_SPC\b/ => '--- !ruby/object:SOCMaker::IfcSpc',
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/\bSOCM_INCLUDE\b/ => '--- !ruby/object:SOCMaker::LibInc',
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/\bSOCM_INCLUDE\b/ => '--- !ruby/object:SOCMaker::LibInc',
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/\bSOCM_INST\b/ => '!ruby/object:SOCMaker::CoreInst',
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/\bSOCM_INST\b/ => '!ruby/object:SOCMaker::CoreInst',
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/\bSOCM_IFC\b/ => '!ruby/object:SOCMaker::IfcDef',
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/\bSOCM_IFC\b/ => '!ruby/object:SOCMaker::IfcDef',
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/\bSOCM_PORT\b/ => '!ruby/object:SOCMaker::IfcPort',
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/\bSOCM_PORT\b/ => '!ruby/object:SOCMaker::IfcPort',
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/\bSOCM_HDL_FILE\b/ => '!ruby/object:SOCMaker::HDLFile',
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/\bSOCM_HDL_FILE\b/ => '!ruby/object:SOCMaker::HDLFile',
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/\bSOCM_PARAM\b/ => '!ruby/object:SOCMaker::Parameter',
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/\bSOCM_PARAM\b/ => '!ruby/object:SOCMaker::Parameter',
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/\bSOCM_SPARAM\b/ => '!ruby/object:SOCMaker::SParameter',
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/\bSOCM_SPARAM\b/ => '!ruby/object:SOCMaker::SParameter',
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/\bSOCM_SENTRY\b/ => '!ruby/object:SOCMaker::SParameterEntry'
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/\bSOCM_SENTRY\b/ => '!ruby/object:SOCMaker::SParameterEntry'
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},
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},
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#
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#
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# $1 provides the white spaces
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# $1 provides the white spaces
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# $2 the name
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# $2 the name
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#
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#
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:YPP_INV_REGEX => /(\s)*-{0,3}\s*!ruby\/object:SOCMaker::([a-zA-Z]+)/,
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:YPP_INV_REGEX => /(\s)*-{0,3}\s*!ruby\/object:SOCMaker::([a-zA-Z]+)/,
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:YPP_INV_LUT => {
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:YPP_INV_LUT => {
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'Conf' => 'SOCM_CONF',
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'Conf' => 'SOCM_CONF',
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'CoreDef' => 'SOCM_CORE',
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'CoreDef' => 'SOCM_CORE',
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'SOCDef' => 'SOCM_SOC',
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'SOCDef' => 'SOCM_SOC',
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'CoreInst' => 'SOCM_INST',
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'CoreInst' => 'SOCM_INST',
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'IfcSpc' => 'SOCM_IFC_SPC',
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'IfcSpc' => 'SOCM_IFC_SPC',
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'IfcDef' => 'SOCM_IFC',
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'IfcDef' => 'SOCM_IFC',
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'IfcPort' => 'SOCM_PORT',
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'IfcPort' => 'SOCM_PORT',
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'HDLFile' => 'SOCM_HDL_FILE',
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'HDLFile' => 'SOCM_HDL_FILE',
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'Parameter' => 'SOCM_PARAM',
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'Parameter' => 'SOCM_PARAM',
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'SParameter' => 'SOCM_SPARAM',
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'SParameter' => 'SOCM_SPARAM',
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'SParameterEntry' => 'SOCM_SENTRY',
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'SParameterEntry' => 'SOCM_SENTRY',
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'LibInc' => 'SOCM_INCLUDE'
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'LibInc' => 'SOCM_INCLUDE'
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},
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},
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# used to split yaml files
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# used to split yaml files
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#
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#
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:YPP_SPLIT_REGEX => /^\s*---\s*!ruby\/(object|object):SOCMaker/,
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:YPP_SPLIT_REGEX => /^\s*---\s*!ruby\/(object|object):SOCMaker/,
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:COMMENT_REGEX => /([^#]*)(#.*)?/,
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:COMMENT_REGEX => /([^#]*)(#.*)?/,
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|
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:EMPTY_CMD_REGEX => /(\s*)(.*)/,
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:EMPTY_CMD_REGEX => /(\s*)(.*)/,
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|
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:LIC =>
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:LIC =>
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"""
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"""
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Copyright (C) 2014 Christian Haettich - feddischson [ at ] opencores.org
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Copyright (C) 2014 Christian Haettich - feddischson [ at ] opencores.org
|
|
|
This program is free software: you can redistribute it and/or modify
|
This program is free software: you can redistribute it and/or modify
|
it under the terms of the GNU General Public License as published by
|
it under the terms of the GNU General Public License as published by
|
the Free Software Foundation, either version 3 of the License, or
|
the Free Software Foundation, either version 3 of the License, or
|
(at your option) any later version.
|
(at your option) any later version.
|
|
|
This program is distributed in the hope that it will be useful,
|
This program is distributed in the hope that it will be useful,
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
GNU General Public License for more details.
|
GNU General Public License for more details.
|
|
|
You should have received a copy of the GNU General Public License
|
You should have received a copy of the GNU General Public License
|
along with this program. If not, see .
|
along with this program. If not, see .
|
"""
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"""
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|
|
|
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}
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}
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end
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end
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|
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def [](y)
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def [](y)
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@data.merge( @data_ro )[y]
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@data.merge( @data_ro )[y]
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end
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end
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|
|
def []=(y, value)
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def []=(y, value)
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@data[y] = value
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@data[y] = value
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end
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end
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@@inst = nil
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@@inst = nil
|
|
|
|
|
end
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end
|
|
|
end
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end
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|
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|
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# vim: noai:ts=2:sw=2
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# vim: noai:ts=2:sw=2
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|
|
