###############################################################
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###############################################################
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#
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#
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# File: hdl_coder.rb
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# File: hdl_coder.rb
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#
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#
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# Author: Christian Hättich
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# Author: Christian Hättich
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#
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#
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# Project: System-On-Chip Maker
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# Project: System-On-Chip Maker
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#
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#
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# Target: Linux / Windows / Mac
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# Target: Linux / Windows / Mac
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#
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#
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# Language: ruby
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# Language: ruby
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#
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#
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#
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#
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###############################################################
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###############################################################
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#
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#
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#
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#
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# Copyright (C) 2014 Christian Hättich - feddischson [ at ] opencores.org
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# Copyright (C) 2014 Christian Hättich - feddischson [ at ] opencores.org
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#
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#
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# This program is free software: you can redistribute it and/or modify
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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# (at your option) any later version.
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#
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#
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# This program is distributed in the hope that it will be useful,
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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# GNU General Public License for more details.
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#
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#
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# You should have received a copy of the GNU General Public License
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see .
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# along with this program. If not, see .
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#
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#
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#
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#
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###############################################################
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###############################################################
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#
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#
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# Description:
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# Description:
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# This file contains two HDL-coders:
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# This file contains two HDL-coders:
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# - VHDLCoder
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# - VHDLCoder
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# - VerilogCoder (not implemented, yet)
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# - VerilogCoder (not implemented, yet)
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#
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#
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#
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#
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#
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#
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###############################################################
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###############################################################
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module SOCMaker
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module SOCMaker
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class HDLCoder
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class HDLCoder
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def initialize
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def initialize
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@decl_part = ""; # declaration
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@decl_part = ""; # declaration
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@asgn_part = ""; # assignment
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@asgn_part = ""; # assignment
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@inst_part = ""; # instantiation
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@inst_part = ""; # instantiation
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end
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end
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end
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end
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class VerilogCoder < HDLCoder
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class VerilogCoder < HDLCoder
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#TODO
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#TODO
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#
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#
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def filename( name )
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return name + ".v"
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end
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end
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end
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class VHDLCoder < HDLCoder
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class VHDLCoder < HDLCoder
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#
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#
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# Add a component declaration to the declaration-string @decl_part
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# Add a component declaration to the declaration-string @decl_part
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# This for example looks like
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# This for example looks like
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# component <> is
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# component <> is
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# generic(
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# generic(
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# g1 : ...
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# g1 : ...
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# g2 : ...
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# g2 : ...
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# ...
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# ...
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# );
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# );
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# port(
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# port(
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# p1 : ...
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# p1 : ...
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# p2 : ...
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# p2 : ...
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# p3 : ...
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# p3 : ...
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# ...
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# ...
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# )
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# )
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# end component <>;
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# end component <>;
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#
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#
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# In addition, we add some VHDL comments (author, mail, license)
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# In addition, we add some VHDL comments (author, mail, license)
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#
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#
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def add_core_declaration( core_name, core_spec )
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def add_core_component( core_name, core_spec )
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@decl_part << "--\n"
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@decl_part << "--\n"
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@decl_part << "-- core author: #{core_spec.author} - #{core_spec.authormail}\n"
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@decl_part << "-- core author: #{core_spec.author} - #{core_spec.authormail}\n"
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@decl_part << "-- license: #{core_spec.license}\n"
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@decl_part << "-- license: #{core_spec.license}\n"
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@decl_part << "--\n"
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@decl_part << "--\n"
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@decl_part << "component #{core_spec.toplevel} is\n"
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@decl_part << "component #{core_spec.toplevel} is\n"
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generic_str = entity_generic_str( core_spec );
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generic_str = entity_generic_str( core_spec );
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@decl_part << "generic ( #{ generic_str });\n" if generic_str.size > 0
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@decl_part << "generic ( #{ generic_str });\n" if generic_str.size > 0
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@decl_part << "port( \n" << entity_port_str( core_spec ) <<" );\n"
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@decl_part << "port( \n" << entity_port_str( core_spec ) <<" );\n"
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@decl_part << "end component #{core_spec.toplevel};\n"
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@decl_part << "end component #{core_spec.toplevel};\n"
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entity_generic_str( core_spec )
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#entity_generic_str( core_spec )
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end
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end
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def filename( name )
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return name + ".vhd"
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end
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def entity_generic_str( core )
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def entity_generic_str( core )
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generic_str = ""
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generic_str = ""
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core.generics do |gen_name, gen_type, gen_val, is_last|
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core.generics do |gen_name, gen_type, gen_val, is_last|
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generic_str << gen_name << " : " << gen_type << " := " << gen_val.to_s
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generic_str << gen_name << " : " << gen_type << " := " << gen_val.to_s
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generic_str << ";" unless is_last
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generic_str << ";" unless is_last
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generic_str << "\n"
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generic_str << "\n"
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end
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end
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return generic_str
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return generic_str
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end
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end
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#
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#
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# Create a string, which lists all signals of 'core'
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# Create a string, which lists all signals of 'core'
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# We iterate over all interface:
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# We iterate over all interface:
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# For each interface, we iterate over all ports:
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# For each interface, we iterate over all ports:
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# For each port, we lookup the definition in the 'soc_lib' and
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# For each port, we lookup the definition in the 'soc_lib' and
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# add the VHDL code according to the definition as string to
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# add the VHDL code according to the definition as string to
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# port_string
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# port_string
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#
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#
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def entity_port_str( core )
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def entity_port_str( core )
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port_string = ""
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port_string = ""
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core.ports do |port_name, port_dir, port_len, is_last |
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core.ports do |port_name, port_dir, port_len, is_last |
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# The string we are add in every iteration looks for example like
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# The string we are add in every iteration looks for example like
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# myportname1 : out std_logic_vector( 6-1 downto 0 )
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# myportname1 : out std_logic_vector( 6-1 downto 0 )
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# or
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# or
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# myportname2 : in std_logic
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# myportname2 : in std_logic
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#
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#
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port_string << port_name.to_s << " : "
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port_string << port_name.to_s << " : "
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puts port_name.to_s + ": dir: " + port_dir.to_s + ", len: " + port_len.to_s
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# port direction
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# port direction
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if port_dir == 2
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if port_dir == 2
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port_string << " inout "
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port_string << " inout "
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elsif port_dir == 1
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elsif port_dir == 1
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port_string << " in "
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port_string << " in "
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else
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else
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port_string << " out "
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port_string << " out "
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end
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end
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# port type / length
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# port type / length
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if( port_len.is_a?( String ) ||
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if( port_len.is_a?( String ) ||
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( port_len.is_a?( Fixnum ) && port_len > 1 )
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( port_len.is_a?( Fixnum ) && port_len > 1 )
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)
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)
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port_string << " std_logic_vector( #{port_len}-1 downto 0 ) "
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port_string << " std_logic_vector( #{port_len}-1 downto 0 ) "
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elsif ( port_len.is_a?( Fixnum ) && port_len == 1 )
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elsif ( port_len.is_a?( Fixnum ) && port_len == 1 )
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port_string << " std_logic "
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port_string << " std_logic "
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else
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else
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puts "FAILED " + port_len
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puts "FAILED " + port_len.to_s #TODO
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end
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end
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# end of the line
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# end of the line
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port_string << ";" unless is_last
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port_string << ";" unless is_last
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port_string << "\n"
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port_string << "\n"
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end
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end
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return port_string
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return port_string
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end
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end
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def add_core_inst( inst_name, inst )
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def add_core_instance( inst_name, inst )
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@inst_part << inst_name << " : " << inst.defn.toplevel << "\n"
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@inst_part << inst_name << " : " << inst.defn.toplevel << "\n"
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generic_str = ""
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generic_str = ""
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inst.generics do |generic, type, value, is_last|
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inst.generics do |generic, type, value, is_last|
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generic_str << "#{generic} => #{value}"
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generic_str << "#{generic} => #{value}"
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generic_str << "," unless is_last
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generic_str << "," unless is_last
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generic_str << "\n"
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generic_str << "\n"
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end
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end
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@inst_part << "generic map( \n#{generic_str} )\n" if generic_str.size > 0
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@inst_part << "generic map( \n#{generic_str} )\n" if generic_str.size > 0
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port_str = ""
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port_str = ""
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inst.ports do |port_name, length, dir, is_last|
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inst.ports do |port_name, dir, length, is_last|
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port_str << "#{port_name} => #{inst_name}_#{port_name}"
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port_str << "#{port_name} => #{inst_name}_#{port_name}"
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port_str << "," unless is_last
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port_str << "," unless is_last
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port_str << "\n"
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port_str << "\n"
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if length > 1
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if length > 1
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@decl_part << "signal #{inst_name}_#{port_name} : std_logic_vector( #{length}-1 downto 0 );\n"
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@decl_part << "signal #{inst_name}_#{port_name} : std_logic_vector( #{length}-1 downto 0 );\n"
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else
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else
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@decl_part << "signal #{inst_name}_#{port_name} : std_logic;\n"
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@decl_part << "signal #{inst_name}_#{port_name} : std_logic;\n"
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end
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end
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end
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end
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@inst_part << "port map( \n#{port_str} );\n\n\n" if port_str.size > 0
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@inst_part << "port map( \n#{port_str} );\n\n\n" if port_str.size > 0
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end
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end
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def add_ifc_connection( ifc_spec, ifc_name, length, src_inst, dst_inst, src_ifc, dst_ifc )
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###
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#
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# declaration
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def ifc_declaration( ifc_spec, ifc_name, length )
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#
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#
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ifc_spec.ports.each do |port_name, port|
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ifc_spec.ports.each do |port_name, port|
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@decl_part << "signal #{ifc_name}_#{port_name.to_s} : "
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@decl_part << "signal #{ifc_name}_#{port_name.to_s} : "
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if length[ port_name ] > 1
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if length[ port_name ] > 1
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@decl_part << " std_logic_vector( #{length[ port_name ]}-1 downto 0 ) "
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@decl_part << " std_logic_vector( #{length[ port_name ]}-1 downto 0 ) "
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else
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else
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@decl_part << " std_logic "
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@decl_part << " std_logic "
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end
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end
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# end of the line
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# end of the line
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@decl_part << ";\n"
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@decl_part << ";\n"
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end
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end
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end
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def ifc_assignment( ifc_spec, ifc_name, length, src_inst, dst_inst, src_ifc, dst_ifc )
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###
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#
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# assignment
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#
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#
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ifc_spec.ports.each do |port_name, port_dir|
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ifc_spec.ports.each do |port_name, port_dir|
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if port_dir == 0
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if port_dir == 0
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src_inst_sel = src_inst
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src_inst_sel = src_inst
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dst_inst_sel = dst_inst
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dst_inst_sel = dst_inst
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src_ifc_sel = src_ifc
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src_ifc_sel = src_ifc
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dst_ifc_sel = dst_ifc
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dst_ifc_sel = dst_ifc
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else
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else
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src_inst_sel = dst_inst
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src_inst_sel = dst_inst
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dst_inst_sel = src_inst
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dst_inst_sel = src_inst
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src_ifc_sel = dst_ifc
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src_ifc_sel = dst_ifc
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dst_ifc_sel = src_ifc
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dst_ifc_sel = src_ifc
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end
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end
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# length == 0 means, that no
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# length == 0 means, that no
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# signal is assigned to this connection
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# signal is assigned to this connection
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if length[ port_name ] > 0
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if length[ port_name ] > 0
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port_tmp_name = "#{ifc_name}_#{port_name.to_s}"
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port_tmp_name = "#{ifc_name}_#{port_name.to_s}"
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# combine all sources
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# combine all sources
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tmp = "#{port_tmp_name} <= "
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tmp = "#{port_tmp_name} <= "
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assigned = false
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# loop over instances
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# loop over instances
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src_inst_sel.each_with_index do |(inst_name, inst), i|
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src_inst_sel.each_with_index do |(inst_name, inst), i|
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( tmp_name, port) = inst.get_port( src_ifc_sel[ inst_name ], port_name )
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( tmp_name, port) = inst.get_port( src_ifc_sel[ inst_name ], port_name )
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if port != nil
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if port != nil
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tmp << "\"" + "0" * ( length[ port_name ] - port[ :len ] ) + "\" & " if port[ :len ] < length[ port_name ]
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tmp << "\"" + "0" * ( length[ port_name ] - port[ :len ] ) + "\" & " if port[ :len ] < length[ port_name ]
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tmp << "#{inst_name}_#{tmp_name}"
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tmp << "#{inst_name}_#{tmp_name}"
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tmp << " and \n" unless i == src_inst_sel.size-1
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tmp << " and \n" unless i == src_inst_sel.size-1
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assigned = true
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end
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end
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end
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end
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tmp << ";\n"
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tmp << ";\n"
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@asgn_part << tmp
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@asgn_part << tmp if assigned
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puts src_inst_sel.size
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puts tmp
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# assign to destination
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tmp = ""
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tmp = ""
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assigned = false
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# assign to destination
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dst_inst_sel.each_with_index do |(inst_name, inst), i|
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dst_inst_sel.each_with_index do |(inst_name, inst), i|
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if not inst == nil #TODO
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( tmp_name, port) = inst.get_port( dst_ifc_sel[ inst_name ], port_name )
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( tmp_name, port) = inst.get_port( dst_ifc_sel[ inst_name ], port_name )
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if port != nil
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if port != nil
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tmp << "#{inst_name}_#{tmp_name} <= #{port_tmp_name}"
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tmp << "#{inst_name}_#{tmp_name} <= #{port_tmp_name}"
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tmp << "( #{port[ :len ]}-1 downto 0 )" if port[ :len ] > 1
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tmp << "( #{port[ :len ]}-1 downto 0 )" if port[ :len ] > 1
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tmp << ";\n"
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tmp << ";\n"
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assigned = true
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end
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end
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end
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end
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@asgn_part << tmp
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end
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end
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@asgn_part << tmp if assigned
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end
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end
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end
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end
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end
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# TODO: add sig list as argument (or interface list) for entity description
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def get_hdl_code( soc, entity_name )
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def get_entity( soc, entity_name )
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add_toplevel_sig( soc, entity_name )
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add_toplevel_sig( soc, entity_name )
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entity_str = SOCMaker::conf[ :LIC ].split(/\n/).map{ |s| "-- "+s }.join("\n") + "\n"
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entity_str = SOCMaker::conf[ :LIC ].split(/\n/).map{ |s| "-- "+s }.join("\n") + "\n"
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entity_str << "-- Auto-Generated by #{SOCMaker::conf[ :app_name ]} \n"
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entity_str << "-- Auto-Generated by #{SOCMaker::conf[ :app_name ]} \n"
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entity_str << "-- Date: #{Time.now}\n"
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entity_str << "-- Date: #{Time.now}\n"
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entity_str << SOCMaker::conf[ :vhdl_include ] + "\n"
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entity_str << SOCMaker::conf[ :vhdl_include ] + "\n"
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entity_str << "entity #{entity_name} is \n"
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entity_str << "entity #{entity_name} is \n"
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tmp = entity_port_str( soc )
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tmp = entity_port_str( soc )
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entity_str << "port( \n" << tmp << " );\n" if tmp.size > 0
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entity_str << "port( \n" << tmp << " );\n" if tmp.size > 0
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entity_str << "end entity #{entity_name};\n\n\n"
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entity_str << "end entity #{entity_name};\n\n\n"
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entity_str << "ARCHITECTURE IMPL of #{entity_name} is \n"
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entity_str << "ARCHITECTURE IMPL of #{entity_name} is \n"
|
entity_str << @decl_part
|
entity_str << @decl_part
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entity_str << "\n\n"
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entity_str << "\n\n"
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entity_str << "begin"
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entity_str << "begin"
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entity_str << "\n\n"
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entity_str << "\n\n"
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entity_str << "--"
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entity_str << "--"
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entity_str << "-- assignments "
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entity_str << "-- assignments "
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entity_str << "--"
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entity_str << "--"
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entity_str << "\n\n"
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entity_str << "\n\n"
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entity_str << @asgn_part
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entity_str << @asgn_part
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entity_str << "\n\n"
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entity_str << "\n\n"
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entity_str << "--"
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entity_str << "--"
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entity_str << "-- instances "
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entity_str << "-- instances "
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entity_str << "--"
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entity_str << "--"
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entity_str << "\n\n"
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entity_str << "\n\n"
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entity_str << @inst_part
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entity_str << @inst_part
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entity_str << "end ARCHITECTURE IMPL;"
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entity_str << "end ARCHITECTURE IMPL;"
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return entity_str
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return entity_str
|
end
|
end
|
|
|
def add_toplevel_sig( soc, entity_name )
|
def add_toplevel_sig( soc, entity_name )
|
soc.ports do |port_name, length, dir, is_last|
|
soc.ports do |port_name, dir, length, is_last|
|
|
if dir == 0
|
@asgn_part << "#{port_name} <= #{entity_name}_#{port_name}"
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@asgn_part << "#{port_name} <= #{entity_name}_#{port_name}"
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@asgn_part << "," unless is_last
|
else
|
@asgn_part << "\n"
|
@asgn_part << "#{entity_name}_#{port_name} <= #{port_name} "
|
|
end
|
|
@asgn_part << ";\n"
|
if length > 1
|
if length > 1
|
@decl_part << "signal #{entity_name}_#{port_name} : std_logic_vector( #{length}-1 downto 0 );\n"
|
@decl_part << "signal #{entity_name}_#{port_name} : std_logic_vector( #{length}-1 downto 0 );\n"
|
else
|
else
|
@decl_part << "signal #{entity_name}_#{port_name} : std_logic;\n"
|
@decl_part << "signal #{entity_name}_#{port_name} : std_logic;\n"
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
def asgn_str( ifc_spec, con, ifc_name, core1, core1_name, core2, core2_name )
|
def asgn_str( ifc_spec, con, ifc_name, core1, core1_name, core2, core2_name )
|
port_string = ""
|
port_string = ""
|
|
|
{ core1 => [ con[ :ifc1 ], :src1 ],
|
{ core1 => [ con[ :ifc1 ], :src1 ],
|
core2 => [ con[ :ifc2 ], :src2 ] }.each do| core, tmp |
|
core2 => [ con[ :ifc2 ], :src2 ] }.each do| core, tmp |
|
|
|
core.ports( tmp[0] ) do | port_spec_name, port_name, port_dir |
|
core.ports( tmp[0] ) do | port_spec_name, port_name, port_dir |
|
|
|
if port_dir == 0
|
if port_dir == 0
|
port_string << "#{ifc_name}_#{port_spec_name}"
|
port_string << "#{ifc_name}_#{port_spec_name}"
|
port_string << " <= "
|
port_string << " <= "
|
port_string << "#{con[ tmp[1] ]}_#{port_name}"
|
port_string << "#{con[ tmp[1] ]}_#{port_name}"
|
port_string << ";\n"
|
port_string << ";\n"
|
else
|
else
|
port_string << "#{con[ tmp[1] ]}_#{port_name}"
|
port_string << "#{con[ tmp[1] ]}_#{port_name}"
|
port_string << " <= "
|
port_string << " <= "
|
port_string << "#{ifc_name}_#{port_spec_name }"
|
port_string << "#{ifc_name}_#{port_spec_name }"
|
port_string << ";\n"
|
port_string << ";\n"
|
end
|
end
|
end
|
end
|
|
|
end
|
end
|
|
|
return port_string
|
return port_string
|
end
|
end
|
|
|
|
|
|
|
|
|
|
|
end
|
end
|
end
|
end
|
|
|
# vim: noai:ts=2:sw=2
|
# vim: noai:ts=2:sw=2
|
|
|
