###############################################################
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###############################################################
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#
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#
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# File: hdl_file.rb
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# File: hdl_file.rb
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#
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#
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# Author: Christian Hättich
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# Author: Christian Hättich
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#
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#
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# Project: System-On-Chip Maker
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# Project: System-On-Chip Maker
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#
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#
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# Target: Linux / Windows / Mac
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# Target: Linux / Windows / Mac
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#
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#
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# Language: ruby
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# Language: ruby
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#
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#
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#
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#
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###############################################################
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###############################################################
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#
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#
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#
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#
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# Copyright (C) 2014 Christian Hättich - feddischson [ at ] opencores.org
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# Copyright (C) 2014 Christian Hättich - feddischson [ at ] opencores.org
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#
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#
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# This program is free software: you can redistribute it and/or modify
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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# (at your option) any later version.
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#
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#
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# This program is distributed in the hope that it will be useful,
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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# GNU General Public License for more details.
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#
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#
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# You should have received a copy of the GNU General Public License
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see .
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# along with this program. If not, see .
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#
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#
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#
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#
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###############################################################
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###############################################################
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#
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#
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# Description:
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# Description:
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#
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#
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#
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#
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# A small classes, used to group information
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# A small classes, used to group information
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# and to verify, auto-correct and auto-complete
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# and to verify, auto-correct and auto-complete
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# this information:
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# this information:
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# The class represents an high-level-description (HDL) file.
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# The class represents an high-level-description (HDL) file.
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# The two supported file-types are *.vhdl and *.v, whose information
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# The two supported file-types are *.vhdl and *.v, whose information
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# is stored in @type ('verilog' or 'vhdl').
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# is stored in @type ('verilog' or 'vhdl').
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# A @path is mandatory and defines, where the file is located.
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# A @path is mandatory and defines, where the file is located.
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# In addition, is is used for auto-detecting the file-type (if not given).
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# In addition, is is used for auto-detecting the file-type (if not given).
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# There are three flags:
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# There are three flags:
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# - use_syn (use in synthesis)
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# - use_syn (use in synthesis)
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# - use_sys_sim (use in system simulation)
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# - use_sys_sim (use in system simulation)
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# - use_mod_sim (use in module simulation)
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# - use_mod_sim (use in module simulation)
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# These flags are not used at the moment and reserved for
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# These flags are not used at the moment and reserved for
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# future implementation.
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# future implementation.
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#
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#
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#
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#
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###############################################################
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###############################################################
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module SOCMaker
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module SOCMaker
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class HDLFile
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class HDLFile
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include ERR
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include ERR
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attr_accessor :path
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attr_accessor :path
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attr_accessor :use_syn
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attr_accessor :use_syn
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attr_accessor :use_sys_sim
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attr_accessor :use_sys_sim
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attr_accessor :use_mod_sim
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attr_accessor :use_mod_sim
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attr_accessor :type
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attr_accessor :type
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def initialize( path, options = {} )
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def initialize( path, optional = {} )
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init_with( { 'path' => path }.merge( options ) )
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init_with( { 'path' => path }.merge( optional ) )
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end
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end
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def encode_with( coder )
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def encode_with( coder )
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%w[ path use_syn use_sys_sim use_mod_sim type ].
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%w[ path use_syn use_sys_sim use_mod_sim type ].
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each { |v| coder[ v ] = instance_variable_get "@#{v}" }
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each { |v| coder[ v ] = instance_variable_get "@#{v}" }
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end
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end
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def init_with( coder )
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def init_with( coder )
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serr_if( !( coder.is_a?( Hash ) ||
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serr_if( !( coder.is_a?( Hash ) ||
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coder.is_a?( Psych::Coder ) ),
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coder.is_a?( Psych::Coder ) ),
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'coder is not given as Hash neither as Psych::Coder' )
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'coder is not given as Hash neither as Psych::Coder' )
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# check path
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# check path
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serr_if( coder[ 'path' ] == nil, 'no filepath specified' )
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serr_if( coder[ 'path' ] == nil, 'no filepath specified' )
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@path = coder[ 'path' ]
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@path = coder[ 'path' ]
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verr_if( !@path.is_a?( String ), 'path must be of type string' )
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verr_if( !@path.is_a?( String ), 'path must be of type string' )
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# auto-complete to 'true'
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# auto-complete to 'true'
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@use_syn = coder[ 'use_syn' ] || true
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@use_syn = coder[ 'use_syn' ] || true
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@use_sys_sim = coder[ 'use_sys_sim' ] || true
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@use_sys_sim = coder[ 'use_sys_sim' ] || true
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@use_mod_sim = coder[ 'use_mod_sim' ] || true
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@use_mod_sim = coder[ 'use_mod_sim' ] || true
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# ensure, that the thee use... fields are boolean
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# ensure, that the thee use... fields are boolean
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verr_if( !!@use_syn != @use_syn, 'use_syn field must be true of false' )
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verr_if( !!@use_syn != @use_syn, 'use_syn field must be true of false' )
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verr_if( !!@use_sys_sim != @use_sys_sim, 'use_sys_sim field must be true of false' )
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verr_if( !!@use_sys_sim != @use_sys_sim, 'use_sys_sim field must be true of false' )
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verr_if( !!@use_mod_sim != @use_mod_sim, 'use_mod_sim field must be true of false' )
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verr_if( !!@use_mod_sim != @use_mod_sim, 'use_mod_sim field must be true of false' )
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# if the file-type is not given, we try to auto-detect it
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# if the file-type is not given, we try to auto-detect it
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# *.vhd -> vhdl
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# *.vhd -> vhdl
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# *.v -> verilog
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# *.v -> verilog
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# (see conf[ :vhdl_file_regex ] and
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# (see conf[ :vhdl_file_regex ] and
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# conf[ :verilog_file_regex ] )
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# conf[ :verilog_file_regex ] )
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if coder[ 'type' ] == nil
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if coder[ 'type' ] == nil
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if @path =~ SOCMaker::conf[ :vhdl_file_regex ]
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if @path =~ SOCMaker::conf[ :vhdl_file_regex ]
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SOCMaker::logger.warn "Auto-detected vhdl file type for #{ @path }"
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SOCMaker::logger.warn "Auto-detected vhdl file type for #{ @path }"
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@type = 'vhdl'
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@type = 'vhdl'
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elsif @path =~ SOCMaker::conf[ :verilog_file_regex ]
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elsif @path =~ SOCMaker::conf[ :verilog_file_regex ]
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SOCMaker::logger.warn "Auto-detected verilog file type for #{ @path }"
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SOCMaker::logger.warn "Auto-detected verilog file type for #{ @path }"
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@type = 'verilog'
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@type = 'verilog'
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else
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else
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verr_if( true, 'Cant auto-detect file type for "' + path + '"' )
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verr_if( true, 'Cant auto-detect file type for "' + path + '"' )
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end
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end
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else
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else
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# if the file-type is given, ensure, that it is either 'vhdl' or 'verilog'
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# if the file-type is given, ensure, that it is either 'vhdl' or 'verilog'
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verr_if( !SOCMaker::conf[ :hdl_type_regex ].match( coder[ 'type' ] ),
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verr_if( !SOCMaker::conf[ :hdl_type_regex ].match( coder[ 'type' ] ),
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"The type must be 'vhdl' or 'verilog'",
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"The type must be 'vhdl' or 'verilog'",
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instance: @path,
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instance: @path,
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field: 'type' )
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field: 'type' )
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@type = coder[ 'type' ]
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@type = coder[ 'type' ]
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end
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end
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end
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end
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def ==(o)
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def ==(o)
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o.class == self.class &&
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o.class == self.class &&
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o.path == self.path &&
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o.path == self.path &&
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o.use_syn == self.use_syn &&
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o.use_syn == self.use_syn &&
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o.use_sys_sim == self.use_sys_sim &&
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o.use_sys_sim == self.use_sys_sim &&
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o.use_mod_sim == self.use_mod_sim &&
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o.use_mod_sim == self.use_mod_sim &&
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o.type == self.type
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o.type == self.type
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end
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end
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end
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end
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end
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end
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# vim: noai:ts=2:sw=2
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# vim: noai:ts=2:sw=2
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