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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_ctrl.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134

	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`

`opencores.org`	`opencores.org`
`Mos6502`	`Mos6502`
`T6502`	`T6502`
`ctrl default`	`ctrl default`






`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`configuration`
`ctrl_default`


`dest_dir`
`io_ports`












`gen_verilog`	`gen_verilog`
`104.0`	`104.0`
`none`	`none`
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.ctrl`	`T6502_ctrl`


`dest_dir`
`../verilog`

















`fs-common`	`fs-common`



`../verilog/top.rtl`	`../verilog/top.rtl`
`verilogSourcefragment`	`verilogSourcefragment`








`fs-sim`	`fs-sim`



`../verilog/copyright.v`	`../verilog/copyright.v`
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/common/top.ctrl`	`../verilog/common/T6502_ctrl`
`verilogSourcemodule`	`verilogSourcemodule`







`fs-syn`	`fs-syn`



`../verilog/copyright.v`	`../verilog/copyright.v`
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/common/top.ctrl`	`../verilog/common/T6502_ctrl`
`verilogSourcemodule`	`verilogSourcemodule`




























`Hierarchical`	`Hierarchical`


`spirit:library="Mos6502"`	`spirit:library="Mos6502"`
`spirit:name="T6502"`	`spirit:name="T6502"`
`spirit:version="ctrl.design"/>`	`spirit:version="ctrl.design"/>`





`verilog`	`verilog`


`spirit:library="Testbench"`	`spirit:library="Testbench"`
`spirit:name="toolflow"`	`spirit:name="toolflow"`
`spirit:version="verilog"/>`	`spirit:version="verilog"/>`








`commoncommon`	`commoncommon`
`Verilog`	`Verilog`

`fs-common`	`fs-common`



`sim:Simulation:`	`sim:Simulation:`
`Verilog`	`Verilog`

`fs-sim`	`fs-sim`




`syn:Synthesis:`	`syn:Synthesis:`
`Verilog`	`Verilog`

`fs-syn`	`fs-syn`





`doc`	`doc`


`spirit:library="Testbench"`	`spirit:library="Testbench"`
`spirit:name="toolflow"`	`spirit:name="toolflow"`
`spirit:version="documentation"/>`	`spirit:version="documentation"/>`

`:Documentation:`	`:Documentation:`
`Verilog`	`Verilog`










`VEC_TABLE8'hff`	`VEC_TABLE8'hff`



`PG0_WIDTH8`	`PG0_WIDTH8`
`PG0_ADDR7`	`PG0_ADDR7`

`PG0_WORDS128`	`PG0_WORDS128`

`PG0_WRITETHRU0`	`PG0_WRITETHRU0`


`PG0_DEFAULT8'hff`












`clk`	`clk`
`wire`	`wire`
`in`	`in`




`cpu_pg0_data`	`cpu_pg0_data`
`wire`	`wire`
`out70`	`out70`





`pg00_ram_rd`	`pg00_ram_rd`
`wire`	`wire`
`out`	`out`




`pg00_ram_l_wr`	`pg00_ram_l_wr`
`wire`	`wire`
`out`	`out`




`pg00_ram_h_wr`	`pg00_ram_h_wr`
`wire`	`wire`
`out`	`out`










`io_module_pic_irq_in`	`io_module_pic_irq_in`
`wire`	`wire`
`out70`	`out70`







`io_module_vic_irq_in`	`io_module_vic_irq_in`
`wire`	`wire`
`out70`	`out70`










`mem_rdata`	`mem_rdata`
`wire`	`wire`
`out150`	`out150`





`mem_wdata`	`mem_wdata`
`wire`	`wire`
`in150`	`in150`







`pg0_add`	`pg0_add`
`wire`	`wire`
`in70`	`in70`




`mem_addr`	`mem_addr`
`wire`	`wire`
`in00`	`in00`




`mem_cs`	`mem_cs`
`wire`	`wire`
`in`	`in`





`mem_wr`	`mem_wr`
`wire`	`wire`
`in`	`in`



`pg0_wr`	`pg0_wr`
`wire`	`wire`
`in`	`in`



`mem_rd`	`mem_rd`
`wire`	`wire`
`in`	`in`




`pg0_rd`	`pg0_rd`
`wire`	`wire`
`in`	`in`







`timer_irq`	`timer_irq`
`wire`	`wire`
`in10`	`in10`




`rx_irq`	`rx_irq`
`wire`	`wire`
`in`	`in`



`tx_irq`	`tx_irq`
`wire`	`wire`
`in`	`in`



`ps2_data_avail`	`ps2_data_avail`
`wire`	`wire`
`in`	`in`




`ext_irq_in`	`ext_irq_in`
`wire`	`wire`
`in20`	`in20`

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_ctrl.xml] - Diff between revs 133 and 134