URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_def.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134

	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`

`opencores.org`	`opencores.org`
`Mos6502`	`Mos6502`
`T6502`	`T6502`
`def default`	`def default`



`slave_clk`	`slave_clk`





`clk`	`clk`
`clk`	`clk`





`slave_reset`	`slave_reset`





`reset`	`reset`
`reset`	`reset`










`jtag`	`jtag`





`shiftcapture_dr_clk`	`shiftcapture_dr_clk`
`jtag_shiftcapture_dr_clk`	`jtag_shiftcapture_dr_clk`




`test_logic_reset`	`test_logic_reset`
`jtag_test_logic_reset`	`jtag_test_logic_reset`



`capture_dr`	`capture_dr`
`jtag_capture_dr`	`jtag_capture_dr`



`shift_dr`	`shift_dr`
`jtag_shift_dr`	`jtag_shift_dr`



`update_dr_clk`	`update_dr_clk`
`jtag_update_dr_clk`	`jtag_update_dr_clk`




`tdi`	`tdi`
`jtag_tdi`	`jtag_tdi`



`tdo`	`tdo`
`jtag_tdo`	`jtag_tdo`



`select`	`select`
`jtag_select`	`jtag_select`















`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`configuration`
`default`


`dest_dir`
`io_ports`






`gen_verilog`	`gen_verilog`
`104.0`	`104.0`
`none`	`none`
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top`	`T6502_def`


`dest_dir`
`../verilog`




















`fs-common`	`fs-common`



`../verilog/top.rtl`	`../verilog/top.rtl`
`verilogSourcefragment`	`verilogSourcefragment`








`fs-sim`	`fs-sim`



`../verilog/copyright.v`	`../verilog/copyright.v`
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/common/top`	`../verilog/common/T6502_def`
`verilogSourcemodule`	`verilogSourcemodule`







`fs-syn`	`fs-syn`



`../verilog/syn.v`	`../verilog/syn.v`
`verilogSourceinclude`	`verilogSourceinclude`


















`CPU_ADD16`	`CPU_ADD16`
`VEC_TABLE8'hff`	`VEC_TABLE8'hff`
`ROM_DEFAULT16'hffff`
`BOOT_ROM_WIDTH16`	`BOOT_ROM_WIDTH16`
`ROM_WRITETHRU0`	`ROM_WRITETHRU0`









`Hierarchical`	`Hierarchical`


`spirit:library="Mos6502"`	`spirit:library="Mos6502"`
`spirit:name="T6502"`	`spirit:name="T6502"`
`spirit:version="def.design"/>`	`spirit:version="def.design"/>`




`verilog`	`verilog`


`spirit:library="Testbench"`	`spirit:library="Testbench"`
`spirit:name="toolflow"`	`spirit:name="toolflow"`
`spirit:version="verilog"/>`	`spirit:version="verilog"/>`








`commoncommon`	`commoncommon`
`Verilog`	`Verilog`




`sim:Simulation:`	`sim:Simulation:`
`Verilog`	`Verilog`

`fs-sim`	`fs-sim`



`syn:Synthesis:`	`syn:Synthesis:`
`Verilog`	`Verilog`

`fs-sim`	`fs-sim`




`syn2:Synthesis:`	`syn2:Synthesis:`
`Verilog`	`Verilog`

`fs-syn`	`fs-syn`







`doc`	`doc`


`spirit:library="Testbench"`	`spirit:library="Testbench"`
`spirit:name="toolflow"`	`spirit:name="toolflow"`
`spirit:version="documentation"/>`	`spirit:version="documentation"/>`

`:Documentation:`	`:Documentation:`
`Verilog`	`Verilog`













`ext_addr`	`ext_addr`
`wire`	`wire`
`out231`	`out231`



`ext_wdata`	`ext_wdata`
`wire`	`wire`
`out150`	`out150`



`ext_rdata`	`ext_rdata`
`wire`	`wire`
`in150`	`in150`




`ext_ub`	`ext_ub`
`wire`	`wire`
`out`	`out`


`ext_wait`	`ext_wait`
`wire`	`wire`
`in`	`in`


`ext_lb`	`ext_lb`
`wire`	`wire`
`out`	`out`


`ext_rd`	`ext_rd`
`wire`	`wire`
`out`	`out`


`ext_stb`	`ext_stb`
`wire`	`wire`
`out`	`out`


`ext_wr`	`ext_wr`
`wire`	`wire`
`out`	`out`


`ext_cs`	`ext_cs`
`wire`	`wire`
`out10`	`out10`



`alu_status`	`alu_status`
`wire`	`wire`
`out70`	`out70`


`cts_pad_in`	`cts_pad_in`
`wire`	`wire`
`in`	`in`


`rts_pad_out`	`rts_pad_out`
`wire`	`wire`
`out`	`out`



`gpio_0_out`	`gpio_0_out`
`wire`	`wire`
`out70`	`out70`


`gpio_0_oe`	`gpio_0_oe`
`wire`	`wire`
`out70`	`out70`



`gpio_0_in`	`gpio_0_in`
`wire`	`wire`
`in70`	`in70`


`gpio_1_out`	`gpio_1_out`
`wire`	`wire`
`out70`	`out70`


`gpio_1_oe`	`gpio_1_oe`
`wire`	`wire`
`out70`	`out70`



`gpio_1_in`	`gpio_1_in`
`wire`	`wire`
`in70`	`in70`


`ext_irq_in`	`ext_irq_in`
`wire`	`wire`
`in30`	`in30`





`jsp_data_out`	`jsp_data_out`
`wire`	`wire`
`out70`	`out70`




`wb_jsp_dat_i`	`wb_jsp_dat_i`
`wire`	`wire`
`in70`	`in70`



`biu_wr_strobe`	`biu_wr_strobe`
`wire`	`wire`
`out`	`out`



`wb_jsp_stb_i`	`wb_jsp_stb_i`
`wire`	`wire`
`in`	`in`

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_def.xml] - Diff between revs 133 and 134