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|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
adv_debug_sys
|
adv_debug_sys
|
adv_dbg_if
|
adv_dbg_if
|
cpu0 default
|
cpu0 default
|
|
|
|
|
|
|
|
|
|
|
|
|
elab_verilog
|
|
102.1
|
|
none
|
|
:*Simulation:*
|
|
./tools/verilog/elab_verilog
|
|
|
|
|
|
dest_dir
|
|
io_ports
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog
|
gen_verilog
|
104.0
|
104.0
|
none
|
none
|
:*Simulation:*
|
:*Simulation:*
|
./tools/verilog/gen_verilog
|
./tools/verilog/gen_verilog
|
|
|
|
|
destination
|
destination
|
cpu0
|
cpu0
|
|
|
|
|
dest_dir
|
|
../verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
fs-sim
|
|
|
|
|
|
|
../verilog/cpu0_defines.v
|
../verilog/cpu0_defines.v
|
verilogSource
|
verilogSource
|
include
|
include
|
|
|
|
|
|
|
|
|
../verilog/adbg_or1k_defines.v
|
../verilog/adbg_or1k_defines.v
|
verilogSource
|
verilogSource
|
include
|
include
|
|
|
|
|
|
|
|
|
|
|
../verilog/adbg_top.v
|
../verilog/adbg_top.v
|
verilogSource
|
verilogSource
|
module
|
module
|
|
|
|
|
|
|
crc32
|
crc32
|
../verilog/adbg_crc32.v
|
../verilog/adbg_crc32.v
|
verilogSource
|
verilogSource
|
module
|
module
|
|
|
|
|
|
|
|
|
or1k_biu
|
or1k_biu
|
../verilog/adbg_or1k_biu.v
|
../verilog/adbg_or1k_biu.v
|
verilogSource
|
verilogSource
|
module
|
module
|
|
|
|
|
|
|
|
|
or1k_module
|
or1k_module
|
../verilog/adbg_or1k_module.v
|
../verilog/adbg_or1k_module.v
|
verilogSource
|
verilogSource
|
module
|
module
|
|
|
|
|
|
|
|
|
or1k_status_reg
|
or1k_status_reg
|
../verilog/adbg_or1k_status_reg.v
|
../verilog/adbg_or1k_status_reg.v
|
verilogSource
|
verilogSource
|
module
|
module
|
|
|
|
|
|
|
|
|
|
|
|
|
bytefifo
|
bytefifo
|
../verilog/adbg_bytefifo.v
|
../verilog/adbg_bytefifo.v
|
verilogSource
|
verilogSource
|
module
|
module
|
|
|
|
|
|
|
syncflop
|
syncflop
|
../verilog/adbg_syncflop.v
|
../verilog/adbg_syncflop.v
|
verilogSource
|
verilogSource
|
module
|
module
|
|
|
|
|
|
|
syncreg
|
syncreg
|
../verilog/adbg_syncreg.v
|
../verilog/adbg_syncreg.v
|
verilogSource
|
verilogSource
|
module
|
module
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
jtag
|
jtag
|
|
|
|
|
spirit:library="adv_debug_sys"
|
spirit:library="adv_debug_sys"
|
spirit:name="adv_dbg_if"
|
spirit:name="adv_dbg_if"
|
spirit:version="jtag_i"/>
|
spirit:version="jtag_i"/>
|
|
|
|
|
|
|
|
|
|
|
cpu0
|
cpu0
|
|
|
|
|
spirit:library="adv_debug_sys"
|
spirit:library="adv_debug_sys"
|
spirit:name="adv_dbg_if"
|
spirit:name="adv_dbg_if"
|
spirit:version="cpu0_i"/>
|
spirit:version="cpu0_i"/>
|
|
|
|
|
|
|
|
|
|
|
verilog
|
verilog
|
|
|
|
|
spirit:library="Testbench"
|
spirit:library="Testbench"
|
spirit:name="toolflow"
|
spirit:name="toolflow"
|
spirit:version="verilog"/>
|
spirit:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
sim:*Simulation:*
|
Verilog
|
Verilog
|
|
|
|
|
fs-sim
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
syn:*Synthesis:*
|
Verilog
|
Verilog
|
|
|
|
|
fs-sim
|
fs-sim
|
|
|
|
|
|
|
|
|
doc
|
doc
|
|
|
|
|
spirit:library="Testbench"
|
spirit:library="Testbench"
|
spirit:name="toolflow"
|
spirit:name="toolflow"
|
spirit:version="documentation"/>
|
spirit:version="documentation"/>
|
|
|
:*Documentation:*
|
:*Documentation:*
|
Verilog
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|