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https://opencores.org/ocsvn/socgen/socgen/trunk
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Rev 134 |
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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opencores.org
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opencores.org
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adv_debug_sys
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adv_debug_sys
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adv_dbg_if
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adv_dbg_if
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cpu0_tb
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cpu0_tb
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gen_verilog
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gen_verilog
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104.0
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104.0
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none
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none
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common
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common
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./tools/verilog/gen_verilog
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./tools/verilog/gen_verilog
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destination
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destination
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top.tb.cpu0
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adv_dbg_if_cpu0_tb
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dest_dir
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../verilog
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top
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JTAG_MODEL_DIVCNT 4'h4
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JTAG_MODEL_DIVCNT 4'h4
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JTAG_MODEL_SIZE 4
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JTAG_MODEL_SIZE 4
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Params
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Params
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spirit:library="adv_debug_sys"
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spirit:library="adv_debug_sys"
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spirit:name="adv_dbg_if"
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spirit:name="adv_dbg_if"
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spirit:version="cpu0_dut.params"/>
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spirit:version="cpu0_dut.params"/>
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Bfm
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Bfm
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spirit:library="adv_debug_sys"
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spirit:library="adv_debug_sys"
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spirit:name="adv_dbg_if"
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spirit:name="adv_dbg_if"
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spirit:version="bfm.design"/>
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spirit:version="bfm.design"/>
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icarus
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icarus
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spirit:library="Testbench"
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:name="toolflow"
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spirit:version="icarus"/>
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spirit:version="icarus"/>
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commoncommon
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commoncommon
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Verilog
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Verilog
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fs-common
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fs-common
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sim:*Simulation:*
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sim:*Simulation:*
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Verilog
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Verilog
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fs-sim
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fs-sim
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lint:*Lint:*
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lint:*Lint:*
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Verilog
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Verilog
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fs-lint
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fs-lint
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fs-common
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fs-common
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../verilog/tb.cpu0
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../verilog/tb.cpu0
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verilogSource
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verilogSource
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fragment
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fragment
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fs-sim
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fs-sim
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../verilog/tb.ext
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../verilog/tb.ext
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verilogSource
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verilogSource
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fragment
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fragment
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../verilog/common/top.tb.cpu0
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../verilog/common/adv_dbg_if_cpu0_tb
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verilogSourcemodule
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verilogSourcemodule
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fs-lint
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fs-lint
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../verilog/common/top.tb.cpu0
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../verilog/common/adv_dbg_if_cpu0_tb
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verilogSourcemodule
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verilogSourcemodule
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