URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [componentCfg.xml] - Diff between revs 134 and 135

Only display areas with differences | Details | Blame | View Log

Rev 134	Rev 135

	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`

`opencores.org`	`opencores.org`
`fpgas`	`fpgas`
`Nexys2_T6502`	`Nexys2_T6502`


`2`	`2`
`_`	`_`
`_`	`_`
`_`	`_`
`VARIANT`	`VARIANT`




	`TestBenches`
	`sim`
	`testbenches`
	`testbench`
	`version`


	`Fpgas`
	`syn`
	`ise`
	`chip`
	`variant`










`/doc`	`/doc`







`vga_font`	`vga_font`
`opencores.org`	`opencores.org`
`fpgas`	`fpgas`
`vga_font`	`vga_font`
`code`	`code`





`vga_startup_screen`	`vga_startup_screen`
`opencores.org`	`opencores.org`
`fpgas`	`fpgas`
`vga_startup_screen`	`vga_startup_screen`
`code`	`code`




`io_irq_2`	`io_irq_2`
`opencores.org`	`opencores.org`
`Mos6502`	`Mos6502`
`io_irq_2`	`io_irq_2`
`code`	`code`





`io_poll_2`	`io_poll_2`
`opencores.org`	`opencores.org`
`Mos6502`	`Mos6502`
`io_poll_2`	`io_poll_2`
`code`	`code`




`irq_2_test`	`irq_2_test`
`opencores.org`	`opencores.org`
`Mos6502`	`Mos6502`
`irq_2_test`	`irq_2_test`
`code`	`code`






`kim_2`	`kim_2`
`opencores.org`	`opencores.org`
`Mos6502`	`Mos6502`
`kim_2`	`kim_2`
`code`	`code`





`table_tim1`	`table_tim1`
`opencores.org`	`opencores.org`
`Mos6502`	`Mos6502`
`table_tim1`	`table_tim1`
`code`	`code`





`tim_2`	`tim_2`
`opencores.org`	`opencores.org`
`Mos6502`	`Mos6502`
`tim_2`	`tim_2`
`code`	`code`











`default`	`default`
`default`	`default`
`default_tb`	`default_tb`
`default_lint`	`default_lint`

`RAM_WORDS2048`	`RAM_WORDS2048`
`RAM_ADD11`	`RAM_ADD11`
`ROM_WORDS128`	`ROM_WORDS128`
`ROM_ADD7`	`ROM_ADD7`
`PROG_ROM_WORDS128`	`PROG_ROM_WORDS128`
`PROG_ROM_ADD7`	`PROG_ROM_ADD7`
`VEC_TABLE8'hff`	`VEC_TABLE8'hff`
`CLOCK_FREQ50`	`CLOCK_FREQ50`
`CLOCK_PLL_MULT2`	`CLOCK_PLL_MULT2`
`CLOCK_PLL_DIV4`	`CLOCK_PLL_DIV4`
`CLOCK_PLL_SIZE4`	`CLOCK_PLL_SIZE4`
`CLOCK_SRC0`	`CLOCK_SRC0`
`RESET_SENSE0`	`RESET_SENSE0`
`UART_PRESCALE5'b01100`	`UART_PRESCALE5'b01100`
`UART_PRE_SIZE5`	`UART_PRE_SIZE5`
`UART_DIV0`	`UART_DIV0`
`JTAG_USER1_WIDTH8`	`JTAG_USER1_WIDTH8`
`JTAG_USER1_RESET8'h12`	`JTAG_USER1_RESET8'h12`







`core`	`core`
`core`	`core`

`RAM_WORDS0`	`RAM_WORDS0`
`RAM_ADD0`	`RAM_ADD0`
`ROM_WORDS0`	`ROM_WORDS0`
`ROM_ADD0`	`ROM_ADD0`
`PROG_ROM_WORDS0`	`PROG_ROM_WORDS0`
`PROG_ROM_ADD0`	`PROG_ROM_ADD0`
`VEC_TABLE0'h00`	`VEC_TABLE8'h00`
`UART_PRESCALE0'b00000`	`UART_PRESCALE5'b00000`
`UART_PRE_SIZE0`	`UART_PRE_SIZE5`
`UART_DIV0`	`UART_DIV0`
`JTAG_USER1_WIDTH0`	`JTAG_USER1_WIDTH8`
`JTAG_USER1_RESET0'h00`	`JTAG_USER1_RESET8'h00`






`kim_2`	`kim_2`
`kim_2`	`kim_2`

`ROM_FILE`	`ROM_FILE`
`"opencores.org__Mos6502/sw/table_tim1/table_tim1.abs16"`	`"opencores.org__Mos6502/table_tim1/table_tim1.abs16"`
`ROM_WORDS128`	`ROM_WORDS128`
`ROM_ADD7`	`ROM_ADD7`
`PROG_ROM_FILE`	`PROG_ROM_FILE`
`"opencores.org__Mos6502/sw/kim_2/kim_2.abs16"`	`"opencores.org__Mos6502/kim_2/kim_2.abs16"`
`PROG_ROM_WORDS2048`	`PROG_ROM_WORDS2048`
`PROG_ROM_ADD11`	`PROG_ROM_ADD11`
`STARTUP`	`STARTUP`
`"opencores.org__fpgas/sw/vga_startup_screen/vga_startup_screen.abs"`	`"opencores.org__fpgas/vga_startup_screen/vga_startup_screen.abs"`
`FONT`	`FONT`
`"opencores.org__fpgas/sw/vga_font/vga_font.abs"`	`"opencores.org__fpgas/vga_font/vga_font.abs"`
`RAM_WORDS2048`	`RAM_WORDS2048`
`RAM_ADD11`	`RAM_ADD11`
`VEC_TABLE8'hff`	`VEC_TABLE8'hff`
`CLOCK_FREQ50`	`CLOCK_FREQ50`
`CLOCK_PLL_MULT2`	`CLOCK_PLL_MULT2`
`CLOCK_PLL_DIV4`	`CLOCK_PLL_DIV4`
`CLOCK_PLL_SIZE4`	`CLOCK_PLL_SIZE4`
`CLOCK_SRC0`	`CLOCK_SRC0`
`RESET_SENSE0`	`RESET_SENSE0`
`UART_PRESCALE5'b01100`	`UART_PRESCALE5'b01100`
`UART_PRE_SIZE5`	`UART_PRE_SIZE5`
`UART_DIV0`	`UART_DIV0`
`JTAG_USER1_WIDTH8`	`JTAG_USER1_WIDTH8`
`JTAG_USER1_RESET8'h12`	`JTAG_USER1_RESET8'h12`






`tim_2`	`tim_2`
`tim_2`	`tim_2`

`ROM_FILE`	`ROM_FILE`
`"opencores.org__Mos6502/sw/table_tim1/table_tim1.abs16"`	`"opencores.org__Mos6502/table_tim1/table_tim1.abs16"`
`ROM_WORDS128`	`ROM_WORDS128`
`ROM_ADD7`	`ROM_ADD7`
`PROG_ROM_FILE`	`PROG_ROM_FILE`
`"opencores.org__Mos6502/sw/tim_2/tim_2.abs16"`	`"opencores.org__Mos6502/tim_2/tim_2.abs16"`
`PROG_ROM_WORDS2048`	`PROG_ROM_WORDS2048`
`PROG_ROM_ADD11`	`PROG_ROM_ADD11`
`STARTUP`	`STARTUP`
`"opencores.org__fpgas/sw/vga_startup_screen/vga_startup_screen.abs"`	`"opencores.org__fpgas/vga_startup_screen/vga_startup_screen.abs"`
`FONT`	`FONT`
`"opencores.org__fpgas/sw/vga_font/vga_font.abs"`	`"opencores.org__fpgas/vga_font/vga_font.abs"`
`RAM_WORDS2048`	`RAM_WORDS2048`
`RAM_ADD11`	`RAM_ADD11`
`VEC_TABLE8'hff`	`VEC_TABLE8'hff`
`CLOCK_FREQ50`	`CLOCK_FREQ50`
`CLOCK_PLL_MULT2`	`CLOCK_PLL_MULT2`
`CLOCK_PLL_DIV4`	`CLOCK_PLL_DIV4`
`CLOCK_PLL_SIZE4`	`CLOCK_PLL_SIZE4`
`CLOCK_SRC0`	`CLOCK_SRC0`
`RESET_SENSE0`	`RESET_SENSE0`
`UART_PRESCALE5'b01100`	`UART_PRESCALE5'b01100`
`UART_PRE_SIZE5`	`UART_PRE_SIZE5`
`UART_DIV1`	`UART_DIV1`
`JTAG_USER1_WIDTH8`	`JTAG_USER1_WIDTH8`
`JTAG_USER1_RESET8'h12`	`JTAG_USER1_RESET8'h12`










`Nexys2_T6502/sim`	`Nexys2_T6502/sim`









`Nexys2_T6502_default_tb`	`Nexys2_T6502_default_tb`
`default`	`default`
`default_tb`	`default_tb`

`PERIOD40`	`PERIOD40`
`TIMEOUT100000`	`TIMEOUT100000`


`root.dut.core.T6502.cpucpu`	`root.dut.core.T6502.cpucpu`



`core_def TB.test.dut.core.T6502.cpu.core`	`core_def TB.test.dut.core.T6502.cpu.core`


`io_module_def TB.test.dut.core.T6502.io_module`	`io_module_def TB.test.dut.core.T6502.io_module`



`icarus`	`icarus`
`coverage`	`coverage`






`Nexys2_T6502_default_lint`	`Nexys2_T6502_default_lint`
`default`	`default`
`default_lint`	`default_lint`

`rtl_check`	`rtl_check`














`default`	`default`
`default`	`default`
`Nexys2_T6502_default_lint`	`Nexys2_T6502_default_lint`













`io_irq_2`	`io_irq_2`
`default`	`default`
`Nexys2_T6502_default_tb`	`Nexys2_T6502_default_tb`

`ROM_FILE"NONE"`	`ROM_FILE"NONE"`
`ROM_WORDS128`	`ROM_WORDS128`
`ROM_ADD7`	`ROM_ADD7`
`PROG_ROM_FILE`	`PROG_ROM_FILE`
`"opencores.org__Mos6502/sw/io_irq_2/io_irq_2.abs16"`	`"opencores.org__Mos6502/io_irq_2/io_irq_2.abs16"`
`PROG_ROM_WORDS128`	`PROG_ROM_WORDS128`
`PROG_ROM_ADD7`	`PROG_ROM_ADD7`
`STARTUP`	`STARTUP`
`"opencores.org__fpgas/sw/vga_startup_screen/vga_startup_screen.abs"`	`"opencores.org__fpgas/vga_startup_screen/vga_startup_screen.abs"`
`FONT`	`FONT`
`"opencores.org__fpgas/sw/vga_font/vga_font.abs"`	`"opencores.org__fpgas/vga_font/vga_font.abs"`
`UART_MODEL_CLKCNT5'b11001`	`UART_MODEL_CLKCNT5'b11001`
`UART_MODEL_SIZE5`	`UART_MODEL_SIZE5`
`PERIOD20`	`PERIOD20`





`io_poll_2`	`io_poll_2`
`default`	`default`
`Nexys2_T6502_default_tb`	`Nexys2_T6502_default_tb`

`ROM_FILE"NONE"`	`ROM_FILE"NONE"`
`ROM_WORDS128`	`ROM_WORDS128`
`ROM_ADD7`	`ROM_ADD7`
`PROG_ROM_FILE`	`PROG_ROM_FILE`
`"opencores.org__Mos6502/sw/io_poll_2/io_poll_2.abs16"`	`"opencores.org__Mos6502/io_poll_2/io_poll_2.abs16"`
`PROG_ROM_WORDS128`	`PROG_ROM_WORDS128`
`PROG_ROM_ADD7`	`PROG_ROM_ADD7`
`STARTUP`	`STARTUP`
`"opencores.org__fpgas/sw/vga_startup_screen/vga_startup_screen.abs"`	`"opencores.org__fpgas/vga_startup_screen/vga_startup_screen.abs"`
`FONT`	`FONT`
`"opencores.org__fpgas/sw/vga_font/vga_font.abs"`	`"opencores.org__fpgas/vga_font/vga_font.abs"`
`UART_MODEL_CLKCNT5'b11001`	`UART_MODEL_CLKCNT5'b11001`
`UART_MODEL_SIZE5`	`UART_MODEL_SIZE5`
`PERIOD20`	`PERIOD20`





`irq_2_test`	`irq_2_test`
`default`	`default`
`Nexys2_T6502_default_tb`	`Nexys2_T6502_default_tb`

`ROM_FILE"NONE"`	`ROM_FILE"NONE"`
`ROM_WORDS128`	`ROM_WORDS128`
`ROM_ADD7`	`ROM_ADD7`
`PROG_ROM_FILE`	`PROG_ROM_FILE`
`"opencores.org__Mos6502/sw/irq_2_test/irq_2_test.abs16"`	`"opencores.org__Mos6502/irq_2_test/irq_2_test.abs16"`
`PROG_ROM_WORDS2048`	`PROG_ROM_WORDS2048`
`PROG_ROM_ADD11`	`PROG_ROM_ADD11`
`STARTUP`	`STARTUP`
`"opencores.org__fpgas/sw/vga_startup_screen/vga_startup_screen.abs"`	`"opencores.org__fpgas/vga_startup_screen/vga_startup_screen.abs"`
`FONT`	`FONT`
`"opencores.org__fpgas/sw/vga_font/vga_font.abs"`	`"opencores.org__fpgas/vga_font/vga_font.abs"`
`UART_MODEL_CLKCNT5'b11001`	`UART_MODEL_CLKCNT5'b11001`
`UART_MODEL_SIZE5`	`UART_MODEL_SIZE5`
`PERIOD20`	`PERIOD20`




`kim_2`	`kim_2`
`kim_2`	`kim_2`
`Nexys2_T6502_default_tb`	`Nexys2_T6502_default_tb`

`ROM_FILE`	`ROM_FILE`
`"opencores.org__Mos6502/sw/table_tim1/table_tim1.abs16"`	`"opencores.org__Mos6502/table_tim1/table_tim1.abs16"`
`ROM_WORDS128`	`ROM_WORDS128`
`ROM_ADD7`	`ROM_ADD7`
`PROG_ROM_FILE`	`PROG_ROM_FILE`
`"opencores.org__Mos6502/sw/kim_2/kim_2.abs16"`	`"opencores.org__Mos6502/kim_2/kim_2.abs16"`
`PROG_ROM_WORDS2048`	`PROG_ROM_WORDS2048`
`PROG_ROM_ADD11`	`PROG_ROM_ADD11`
`STARTUP`	`STARTUP`
`"opencores.org__fpgas/sw/vga_startup_screen/vga_startup_screen.abs"`	`"opencores.org__fpgas/vga_startup_screen/vga_startup_screen.abs"`
`FONT`	`FONT`
`"opencores.org__fpgas/sw/vga_font/vga_font.abs"`	`"opencores.org__fpgas/vga_font/vga_font.abs"`
`UART_MODEL_CLKCNT5'b11001`	`UART_MODEL_CLKCNT5'b11001`
`UART_MODEL_SIZE5`	`UART_MODEL_SIZE5`
`PERIOD20`	`PERIOD20`
`TIMEOUT800000`	`TIMEOUT800000`




`jtag`	`jtag`
`default`	`default`
`Nexys2_T6502_default_tb`	`Nexys2_T6502_default_tb`

`ROM_FILE`	`ROM_FILE`
`"opencores.org__Mos6502/sw/table_tim1/table_tim1.abs16"`	`"opencores.org__Mos6502/table_tim1/table_tim1.abs16"`
`ROM_WORDS128`	`ROM_WORDS128`
`ROM_ADD7`	`ROM_ADD7`
`PROG_ROM_FILE`	`PROG_ROM_FILE`
`"opencores.org__Mos6502/sw/kim_2/kim_2.abs16"`	`"opencores.org__Mos6502/kim_2/kim_2.abs16"`
`PROG_ROM_WORDS2048`	`PROG_ROM_WORDS2048`
`PROG_ROM_ADD11`	`PROG_ROM_ADD11`
`STARTUP`	`STARTUP`
`"opencores.org__fpgas/sw/vga_startup_screen/vga_startup_screen.abs"`	`"opencores.org__fpgas/vga_startup_screen/vga_startup_screen.abs"`
`FONT`	`FONT`
`"opencores.org__fpgas/sw/vga_font/vga_font.abs"`	`"opencores.org__fpgas/vga_font/vga_font.abs"`
`UART_MODEL_CLKCNT5'b11001`	`UART_MODEL_CLKCNT5'b11001`
`UART_MODEL_SIZE5`	`UART_MODEL_SIZE5`
`PERIOD20`	`PERIOD20`
`TIMEOUT800000`	`TIMEOUT800000`




`tim_2`	`tim_2`
`default`	`default`
`Nexys2_T6502_default_tb`	`Nexys2_T6502_default_tb`

`ROM_FILE`	`ROM_FILE`
`"opencores.org__Mos6502/sw/table_tim1/table_tim1.abs16"`	`"opencores.org__Mos6502/table_tim1/table_tim1.abs16"`
`ROM_WORDS128`	`ROM_WORDS128`
`ROM_ADD7`	`ROM_ADD7`
`PROG_ROM_FILE`	`PROG_ROM_FILE`
`"opencores.org__Mos6502/sw/tim_2/tim_2.abs16"`	`"opencores.org__Mos6502/tim_2/tim_2.abs16"`
`PROG_ROM_WORDS2048`	`PROG_ROM_WORDS2048`
`PROG_ROM_ADD11`	`PROG_ROM_ADD11`
`STARTUP`	`STARTUP`
`"opencores.org__fpgas/sw/vga_startup_screen/vga_startup_screen.abs"`	`"opencores.org__fpgas/vga_startup_screen/vga_startup_screen.abs"`
`FONT`	`FONT`
`"opencores.org__fpgas/sw/vga_font/vga_font.abs"`	`"opencores.org__fpgas/vga_font/vga_font.abs"`
`UART_DIV1`	`UART_DIV1`
`UART_MODEL_CLKCNT9'h137`	`UART_MODEL_CLKCNT9'h137`
`UART_MODEL_SIZE9`	`UART_MODEL_SIZE9`
`PERIOD20`	`PERIOD20`
`TIMEOUT8000000`	`TIMEOUT8000000`



















`Nexys2_T6502/syn`	`Nexys2_T6502/syn`






`kim_2`
`Nexys2_T6502_kim_2`	`Nexys2_T6502_kim_2`
	`kim_2`
`kim_2`	`kim_2`

`ROM_FILE`	`ROM_FILE`
`"opencores.org__Mos6502/sw/table_tim1/table_tim1.abs16"`	`"opencores.org__Mos6502/table_tim1/table_tim1.abs16"`
`ROM_WORDS128`
`ROM_ADD7`
`PROG_ROM_FILE`
`"opencores.org__Mos6502/sw/kim_2/kim_2.abs16"`
`PROG_ROM_WORDS2048`
`PROG_ROM_ADD11`
`STARTUP`
`"opencores.org__fpgas/sw/vga_startup_screen/vga_startup_screen.abs"`
`FONT`
`"opencores.org__fpgas/sw/vga_font/vga_font.abs"`


`digilentinc.com`
`Nexys2`
`fpga`
`xc3s1200e-fg320-5`





`tim_2`
`Nexys2_T6502_tim_2`
`tim_2`

`ROM_FILE`
`"opencores.org__Mos6502/sw/table_tim1/table_tim1.abs16"`
`ROM_WORDS128`	`ROM_WORDS128`
`ROM_ADD7`	`ROM_ADD7`
`PROG_ROM_FILE`	`PROG_ROM_FILE`
`"opencores.org__Mos6502/sw/tim_2/tim_2.abs16"`	`"opencores.org__Mos6502/kim_2/kim_2.abs16"`
`PROG_ROM_WORDS2048`	`PROG_ROM_WORDS2048`
`PROG_ROM_ADD11`	`PROG_ROM_ADD11`
`STARTUP`	`STARTUP`
`"opencores.org__fpgas/sw/vga_startup_screen/vga_startup_screen.abs"`	`"opencores.org__fpgas/vga_startup_screen/vga_startup_screen.abs"`
`FONT`	`FONT`
`"opencores.org__fpgas/sw/vga_font/vga_font.abs"`	`"opencores.org__fpgas/vga_font/vga_font.abs"`
`UART_DIV1`


`digilentinc.com`
`Nexys2`
`fpga`
`xc3s1200e-fg320-5`












`Nexys2_T6502_kim_2`
`kim_2`
`default`



`ise`	`ise`


`digilentinc.com`	`digilentinc.com`
`Nexys2`	`Nexys2`
`fpga`	`fpga`
`xc3s1200e-fg320-5`	`xc3s1200e-fg320-5`






`Nexys2_T6502_tim_2`
`tim_2`
`default`



`ise`


`digilentinc.com`
`Nexys2`
`fpga`
`xc3s1200e-fg320-5`

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [componentCfg.xml] - Diff between revs 134 and 135