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// //
|
// //
|
// Author : John Eaton Ouabache Designworks //
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// Author : John Eaton Ouabache Designworks //
|
// //
|
// //
|
// Copyright (C) 2010 Authors and OPENCORES.ORG //
|
// Copyright (C) 2010 Authors and OPENCORES.ORG //
|
// //
|
// //
|
// This source file may be used and distributed without //
|
// This source file may be used and distributed without //
|
// restriction provided that this copyright statement is not //
|
// restriction provided that this copyright statement is not //
|
// removed from the file and that any derivative work contains //
|
// removed from the file and that any derivative work contains //
|
// the original copyright notice and the associated disclaimer. //
|
// the original copyright notice and the associated disclaimer. //
|
// //
|
// //
|
// This source file is free software; you can redistribute it //
|
// This source file is free software; you can redistribute it //
|
// and/or modify it under the terms of the GNU Lesser General //
|
// and/or modify it under the terms of the GNU Lesser General //
|
// Public License as published by the Free Software Foundation; //
|
// Public License as published by the Free Software Foundation; //
|
// either version 2.1 of the License, or (at your option) any //
|
// either version 2.1 of the License, or (at your option) any //
|
// later version. //
|
// later version. //
|
// //
|
// //
|
// This source is distributed in the hope that it will be //
|
// This source is distributed in the hope that it will be //
|
// useful, but WITHOUT ANY WARRANTY; without even the implied //
|
// useful, but WITHOUT ANY WARRANTY; without even the implied //
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
|
// PURPOSE. See the GNU Lesser General Public License for more //
|
// PURPOSE. See the GNU Lesser General Public License for more //
|
// details. //
|
// details. //
|
// //
|
// //
|
// You should have received a copy of the GNU Lesser General //
|
// You should have received a copy of the GNU Lesser General //
|
// Public License along with this source; if not, download it //
|
// Public License along with this source; if not, download it //
|
// from http://www.opencores.org/lgpl.shtml //
|
// from http://www.opencores.org/lgpl.shtml //
|
// //
|
// //
|
-->
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
io
|
io
|
io_module
|
io_module
|
def default
|
def default
|
|
|
|
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|
slave_clk
|
slave_clk
|
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|
clk
|
clk
|
clk
|
clk
|
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|
slave_reset
|
slave_reset
|
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|
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|
reset
|
reset
|
reset
|
reset
|
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|
slave_enable
|
slave_enable
|
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|
enable
|
enable
|
enable
|
enable
|
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|
elab_verilog
|
|
102.1
|
|
none
|
|
:*Simulation:*
|
|
./tools/verilog/elab_verilog
|
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configuration
|
|
default
|
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dest_dir
|
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io_ports
|
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gen_registers
|
gen_registers
|
102.1
|
102.1
|
common
|
common
|
none
|
none
|
./tools/regtool/gen_registers
|
./tools/regtool/gen_registers
|
|
|
|
|
bus_intf
|
bus_intf
|
mb
|
mb
|
|
|
|
|
dest_dir
|
dest_dir
|
../verilog
|
../verilog
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|
gen_verilog
|
gen_verilog
|
104.0
|
104.0
|
none
|
none
|
common
|
common
|
./tools/verilog/gen_verilog
|
./tools/verilog/gen_verilog
|
|
|
|
|
destination
|
destination
|
top
|
io_module_def
|
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|
dest_dir
|
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../verilog
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fs-common
|
fs-common
|
|
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|
|
../verilog/top.rtl
|
../verilog/top.rtl
|
verilogSourcefragment
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
fs-sim
|
|
|
|
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|
|
../verilog/copyright.v
|
../verilog/copyright
|
verilogSourceinclude
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
../verilog/common/top
|
../verilog/common/io_module_def
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
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|
dest_dir
|
|
../views/sim/
|
|
verilogSourcelibraryDir
|
|
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|
fs-syn
|
fs-syn
|
|
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|
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|
../verilog/copyright.v
|
../verilog/copyright
|
verilogSourceinclude
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
../verilog/common/top
|
../verilog/common/io_module_def
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
dest_dir
|
|
../views/syn/
|
|
verilogSourcelibraryDir
|
|
|
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|
Hierarchical
|
Hierarchical
|
|
|
|
|
spirit:library="io"
|
spirit:library="io"
|
spirit:name="io_module"
|
spirit:name="io_module"
|
spirit:version="def.design"/>
|
spirit:version="def.design"/>
|
|
|
|
|
|
|
verilog
|
verilog
|
|
|
|
|
spirit:library="Testbench"
|
spirit:library="Testbench"
|
spirit:name="toolflow"
|
spirit:name="toolflow"
|
spirit:version="verilog"/>
|
spirit:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
commoncommon
|
commoncommon
|
Verilog
|
Verilog
|
|
|
|
|
fs-common
|
fs-common
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
sim:*Simulation:*
|
Verilog
|
Verilog
|
|
|
|
|
fs-sim
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
syn:*Synthesis:*
|
Verilog
|
Verilog
|
|
|
|
|
fs-syn
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
doc
|
|
|
|
|
spirit:library="Testbench"
|
spirit:library="Testbench"
|
spirit:name="toolflow"
|
spirit:name="toolflow"
|
spirit:version="documentation"/>
|
spirit:version="documentation"/>
|
|
|
:*Documentation:*
|
:*Documentation:*
|
Verilog
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gpio_0_out
|
gpio_0_out
|
wire
|
wire
|
out
|
out
|
70
|
70
|
|
|
|
|
gpio_0_oe
|
gpio_0_oe
|
wire
|
wire
|
out
|
out
|
70
|
70
|
|
|
|
|
|
|
|
|
gpio_0_in
|
gpio_0_in
|
wire
|
wire
|
in
|
in
|
70
|
70
|
|
|
|
|
gpio_1_out
|
gpio_1_out
|
wire
|
wire
|
out
|
out
|
70
|
70
|
|
|
|
|
gpio_1_oe
|
gpio_1_oe
|
wire
|
wire
|
out
|
out
|
70
|
70
|
|
|
|
|
|
|
|
|
gpio_1_in
|
gpio_1_in
|
wire
|
wire
|
in
|
in
|
70
|
70
|
|
|
|
|
timer_irq
|
timer_irq
|
wire
|
wire
|
out
|
out
|
10
|
10
|
|
|
|
|
pic_irq
|
pic_irq
|
wire
|
wire
|
out
|
out
|
|
|
|
|
pic_nmi
|
pic_nmi
|
wire
|
wire
|
out
|
out
|
|
|
|
|
pic_irq_in
|
pic_irq_in
|
wire
|
wire
|
in
|
in
|
70
|
70
|
|
|
|
|
vic_irq_in
|
vic_irq_in
|
wire
|
wire
|
in
|
in
|
70
|
70
|
|
|
|
|
|
|
cts_pad_in
|
cts_pad_in
|
wire
|
wire
|
in
|
in
|
|
|
|
|
rts_pad_out
|
rts_pad_out
|
wire
|
wire
|
out
|
out
|
|
|
|
|
rx_irq
|
rx_irq
|
wire
|
wire
|
out
|
out
|
|
|
|
|
tx_irq
|
tx_irq
|
wire
|
wire
|
out
|
out
|
|
|
|
|
ps2_data_avail
|
ps2_data_avail
|
wire
|
wire
|
out
|
out
|
|
|
|
|
y_pos
|
y_pos
|
wire
|
wire
|
out
|
out
|
90
|
90
|
|
|
|
|
x_pos
|
x_pos
|
wire
|
wire
|
out
|
out
|
90
|
90
|
|
|
|
|
new_packet
|
new_packet
|
wire
|
wire
|
out
|
out
|
|
|
|
|
ms_mid
|
ms_mid
|
wire
|
wire
|
out
|
out
|
|
|
|
|
ms_right
|
ms_right
|
wire
|
wire
|
out
|
out
|
|
|
|
|
ms_left
|
ms_left
|
wire
|
wire
|
out
|
out
|
|
|
|
|
int_out
|
int_out
|
wire
|
wire
|
out
|
out
|
|
|
|
|
vector
|
vector
|
wire
|
wire
|
out
|
out
|
70
|
70
|
|
|
|
|
|
|
|
|
|
|
ext_ub
|
ext_ub
|
wire
|
wire
|
out
|
out
|
|
|
|
|
ext_stb
|
ext_stb
|
wire
|
wire
|
out
|
out
|
|
|
|
|
|
|
ext_lb
|
ext_lb
|
wire
|
wire
|
out
|
out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
8
|
8
|
mb
|
mb
|
|
|
|
|
mb
|
mb
|
0x00
|
0x00
|
|
|
|
|
gpio
|
gpio
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
|
|
0_out
|
0_out
|
0x02
|
0x02
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
0_oe
|
0_oe
|
0x01
|
0x01
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
0_in
|
0_in
|
0x00
|
0x00
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
|
|
1_out
|
1_out
|
0x06
|
0x06
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
1_oe
|
1_oe
|
0x05
|
0x05
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
1_in
|
1_in
|
0x04
|
0x04
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
|
|
gpio
|
gpio
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
timer
|
timer
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
0_start
|
0_start
|
0x00
|
0x00
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
0_count
|
0_count
|
0x02
|
0x02
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
0_end
|
0_end
|
0x04
|
0x04
|
8
|
8
|
write-only
|
write-only
|
|
|
|
|
|
|
|
|
1_start
|
1_start
|
0x08
|
0x08
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
1_count
|
1_count
|
0x0a
|
0x0a
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
1_end
|
1_end
|
0x0c
|
0x0c
|
8
|
8
|
write-only
|
write-only
|
|
|
|
|
|
|
|
|
|
|
timer
|
timer
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
uart
|
uart
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
xmit_data
|
xmit_data
|
0x00
|
0x00
|
8
|
8
|
write-only
|
write-only
|
|
|
|
|
|
|
rcv_data
|
rcv_data
|
0x02
|
0x02
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
|
|
cntrl
|
cntrl
|
0x04
|
0x04
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
status
|
status
|
0x06
|
0x06
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
|
|
|
|
uart
|
uart
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
pic
|
pic
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
int_in
|
int_in
|
0x00
|
0x00
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
irq_enable
|
irq_enable
|
0x02
|
0x02
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
nmi_enable
|
nmi_enable
|
0x04
|
0x04
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
irq_act
|
irq_act
|
0x06
|
0x06
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
nmi_act
|
nmi_act
|
0x08
|
0x08
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
pic
|
pic
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ps2
|
ps2
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
|
|
data
|
data
|
0x00
|
0x00
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
|
|
wdata_buf
|
wdata_buf
|
0x00
|
0x00
|
8
|
8
|
write-only
|
write-only
|
|
|
|
|
|
|
|
|
status
|
status
|
0x02
|
0x02
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
cntrl
|
cntrl
|
0x04
|
0x04
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
x_pos
|
x_pos
|
0x06
|
0x06
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
y_pos
|
y_pos
|
0x08
|
0x08
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
ps2
|
ps2
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
utimer
|
utimer
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
latch
|
latch
|
0x00
|
0x00
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
count
|
count
|
0x02
|
0x02
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
utimer
|
utimer
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
vga
|
vga
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
ascii_data
|
ascii_data
|
0x00
|
0x00
|
8
|
8
|
write-only
|
write-only
|
|
|
|
|
|
|
add_l
|
add_l
|
0x02
|
0x02
|
8
|
8
|
write-only
|
write-only
|
|
|
|
|
|
|
add_h
|
add_h
|
0x04
|
0x04
|
8
|
8
|
write-only
|
write-only
|
|
|
|
|
|
|
|
|
vadd_l
|
vadd_l
|
0x02
|
0x02
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
vadd_h
|
vadd_h
|
0x04
|
0x04
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
|
|
cntrl
|
cntrl
|
0x06
|
0x06
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
|
|
|
|
char_color
|
char_color
|
0x08
|
0x08
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
|
|
back_color
|
back_color
|
0x0a
|
0x0a
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
cursor_color
|
cursor_color
|
0x0c
|
0x0c
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
vga
|
vga
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ext_mem
|
ext_mem
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
|
|
bank
|
bank
|
0x02
|
0x02
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
wait_st
|
wait_st
|
0x00
|
0x00
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
|
|
mem
|
mem
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
vic
|
vic
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
|
|
int_in
|
int_in
|
0x00
|
0x00
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
irq_enable
|
irq_enable
|
0x02
|
0x02
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
irq_act
|
irq_act
|
0x06
|
0x06
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
irq_vec
|
irq_vec
|
0x08
|
0x08
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
|
|
vic
|
vic
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
17
|
17
|
ext
|
ext
|
|
|
|
|
ext
|
ext
|
0x0000
|
0x0000
|
|
|
|
|
psram
|
psram
|
0x10000
|
0x10000
|
16
|
16
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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