URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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Rev 134 |
Rev 135 |
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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io
|
io
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io_module
|
io_module
|
def default
|
def
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slave_clk
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slave_clk
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clk
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clk
|
clk
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clk
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slave_reset
|
slave_reset
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reset
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reset
|
reset
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|
reset
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slave_enable
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slave_enable
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enable
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|
enable
|
enable
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enable
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gen_registers
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gen_registers
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102.1
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102.1
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common
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:*common:*
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none
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none
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./tools/regtool/gen_registers
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tools/regtool/gen_registers
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bus_intf
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bus_intf
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mb
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mb
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dest_dir
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dest_dir
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../verilog
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../verilog
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gen_verilog
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gen_verilog
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104.0
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104.0
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none
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none
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common
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:*common:*
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./tools/verilog/gen_verilog
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tools/verilog/gen_verilog
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destination
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destination
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io_module_def
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io_module_def
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fs-common
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fs-common
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../verilog/top.rtl
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../verilog/top.rtl
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verilogSourcefragment
|
verilogSourcefragment
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fs-sim
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fs-sim
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../verilog/copyright
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../verilog/copyright
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verilogSourceinclude
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verilogSourceinclude
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../verilog/common/io_module_def
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../verilog/common/io_module_def
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verilogSourcemodule
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verilogSourcemodule
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dest_dir
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dest_dir
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../views/sim/
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../views/sim/
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verilogSourcelibraryDir
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verilogSourcelibraryDir
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fs-syn
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fs-syn
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../verilog/copyright
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../verilog/copyright
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verilogSourceinclude
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verilogSourceinclude
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../verilog/common/io_module_def
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../verilog/common/io_module_def
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verilogSourcemodule
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verilogSourcemodule
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dest_dir
|
dest_dir
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../views/syn/
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../views/syn/
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verilogSourcelibraryDir
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verilogSourcelibraryDir
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Hierarchical
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Hierarchical
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spirit:library="io"
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spirit:name="io_module"
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spirit:version="def.design"/>
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verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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Hierarchical
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Hierarchical
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verilog
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="verilog"/>
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commoncommon
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Verilog
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fs-common
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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|
Verilog
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fs-syn
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common:*common:*
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|
Verilog
|
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fs-common
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sim:*Simulation:*
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Verilog
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fs-sim
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doc
|
syn:*Synthesis:*
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|
Verilog
|
|
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spirit:library="Testbench"
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|
spirit:name="toolflow"
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fs-syn
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spirit:version="documentation"/>
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|
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|
:*Documentation:*
|
|
Verilog
|
|
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doc
|
|
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ipxact:library="Testbench"
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|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
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|
|
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:*Documentation:*
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|
Verilog
|
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gpio_0_out
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wire
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out
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70
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gpio_0_oe
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wire
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out
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70
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clk
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wire
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in
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gpio_0_in
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wire
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in
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70
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gpio_1_out
|
reset
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wire
|
wire
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out
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in
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70
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gpio_1_oe
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|
wire
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out
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70
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enable
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wire
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in
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gpio_1_in
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wire
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in
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70
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timer_irq
|
gpio_0_out
|
wire
|
wire
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out
|
out
|
10
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70
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pic_irq
|
gpio_0_oe
|
wire
|
wire
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out
|
out
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70
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pic_nmi
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|
wire
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out
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pic_irq_in
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|
wire
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in
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70
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vic_irq_in
|
gpio_0_in
|
wire
|
wire
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in
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in
|
70
|
70
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gpio_1_out
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|
wire
|
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out
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70
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cts_pad_in
|
gpio_1_oe
|
wire
|
wire
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in
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out
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70
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rts_pad_out
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|
wire
|
|
out
|
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rx_irq
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|
wire
|
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out
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|
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tx_irq
|
gpio_1_in
|
wire
|
wire
|
out
|
in
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70
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|
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ps2_data_avail
|
timer_irq
|
wire
|
wire
|
out
|
out
|
|
10
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|
|
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|
y_pos
|
pic_irq
|
wire
|
wire
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out
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out
|
90
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|
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x_pos
|
pic_nmi
|
wire
|
wire
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out
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out
|
90
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|
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new_packet
|
pic_irq_in
|
wire
|
wire
|
out
|
in
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|
70
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|
|
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|
ms_mid
|
vic_irq_in
|
wire
|
wire
|
out
|
in
|
|
70
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|
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|
ms_right
|
|
wire
|
|
out
|
|
|
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ms_left
|
cts_pad_in
|
wire
|
wire
|
out
|
in
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|
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int_out
|
rts_pad_out
|
wire
|
wire
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out
|
out
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|
|
|
|
vector
|
rx_irq
|
wire
|
wire
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out
|
out
|
70
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|
|
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tx_irq
|
|
wire
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out
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|
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ps2_data_avail
|
|
wire
|
|
out
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|
y_pos
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|
wire
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out
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|
90
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|
|
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ext_ub
|
x_pos
|
wire
|
wire
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out
|
out
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|
90
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|
|
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|
ext_stb
|
new_packet
|
wire
|
wire
|
out
|
out
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|
|
|
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ms_mid
|
|
wire
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|
out
|
|
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ext_lb
|
ms_right
|
wire
|
wire
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out
|
out
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ms_left
|
|
wire
|
|
out
|
|
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int_out
|
|
wire
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|
out
|
|
|
|
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|
vector
|
|
wire
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out
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|
70
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|
|
|
|
|
|
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|
|
|
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ext_ub
|
|
wire
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out
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|
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|
ext_stb
|
|
wire
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out
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|
|
|
|
|
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ext_lb
|
|
wire
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out
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8
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|
mb
|
|
|
|
|
|
mb
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|
0x00
|
|
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|
|
gpio
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|
0x10
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|
8
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|
|
|
|
|
|
|
|
|
0_out
|
|
0x02
|
|
8
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|
read-write
|
|
|
|
|
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|
0_oe
|
|
0x01
|
|
8
|
|
read-write
|
|
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|
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|
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|
0_in
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|
0x00
|
|
8
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|
read-only
|
|
|
|
|
|
|
|
|
|
|
|
1_out
|
|
0x06
|
|
8
|
|
read-write
|
|
|
|
|
|
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|
1_oe
|
|
0x05
|
|
8
|
|
read-write
|
|
|
|
|
|
|
|
1_in
|
8
|
0x04
|
mb
|
8
|
|
read-only
|
|
|
|
|
|
|
|
|
mb
|
|
0x00
|
|
|
|
|
|
gpio
|
|
0x10
|
|
8
|
|
|
|
|
|
|
|
0_out
|
|
0x02
|
|
8
|
|
read-write
|
|
|
|
|
|
|
|
0_oe
|
|
0x01
|
|
8
|
|
read-write
|
|
|
|
|
|
|
|
0_in
|
|
0x00
|
|
8
|
|
read-only
|
|
|
|
|
|
|
|
|
|
1_out
|
|
0x06
|
|
8
|
|
read-write
|
|
|
|
|
|
|
|
1_oe
|
|
0x05
|
|
8
|
|
read-write
|
|
|
|
|
|
|
|
1_in
|
|
0x04
|
|
8
|
|
read-only
|
|
|
|
|
|
|
|
|
gpio
|
gpio
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
timer
|
timer
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
0_start
|
0_start
|
0x00
|
0x00
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
0_count
|
0_count
|
0x02
|
0x02
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
0_end
|
0_end
|
0x04
|
0x04
|
8
|
8
|
write-only
|
write-only
|
|
|
|
|
|
|
|
|
1_start
|
1_start
|
0x08
|
0x08
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
1_count
|
1_count
|
0x0a
|
0x0a
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
1_end
|
1_end
|
0x0c
|
0x0c
|
8
|
8
|
write-only
|
write-only
|
|
|
|
|
|
|
|
|
|
|
timer
|
timer
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
uart
|
uart
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
xmit_data
|
xmit_data
|
0x00
|
0x00
|
8
|
8
|
write-only
|
write-only
|
|
|
|
|
|
|
rcv_data
|
rcv_data
|
0x02
|
0x02
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
|
|
cntrl
|
cntrl
|
0x04
|
0x04
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
status
|
status
|
0x06
|
0x06
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
|
|
|
|
uart
|
uart
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
pic
|
pic
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
int_in
|
int_in
|
0x00
|
0x00
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
irq_enable
|
irq_enable
|
0x02
|
0x02
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
nmi_enable
|
nmi_enable
|
0x04
|
0x04
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
irq_act
|
irq_act
|
0x06
|
0x06
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
nmi_act
|
nmi_act
|
0x08
|
0x08
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
pic
|
pic
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ps2
|
ps2
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
|
|
data
|
data
|
0x00
|
0x00
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
|
|
wdata_buf
|
wdata_buf
|
0x00
|
0x00
|
8
|
8
|
write-only
|
write-only
|
|
|
|
|
|
|
|
|
status
|
status
|
0x02
|
0x02
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
cntrl
|
cntrl
|
0x04
|
0x04
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
x_pos
|
x_pos
|
0x06
|
0x06
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
y_pos
|
y_pos
|
0x08
|
0x08
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
ps2
|
ps2
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
utimer
|
utimer
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
latch
|
latch
|
0x00
|
0x00
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
count
|
count
|
0x02
|
0x02
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
utimer
|
utimer
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
vga
|
vga
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
ascii_data
|
ascii_data
|
0x00
|
0x00
|
8
|
8
|
write-only
|
write-only
|
|
|
|
|
|
|
add_l
|
add_l
|
0x02
|
0x02
|
8
|
8
|
write-only
|
write-only
|
|
|
|
|
|
|
add_h
|
add_h
|
0x04
|
0x04
|
8
|
8
|
write-only
|
write-only
|
|
|
|
|
|
|
|
|
vadd_l
|
vadd_l
|
0x02
|
0x02
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
vadd_h
|
vadd_h
|
0x04
|
0x04
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
|
|
cntrl
|
cntrl
|
0x06
|
0x06
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
|
|
|
|
char_color
|
char_color
|
0x08
|
0x08
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
|
|
back_color
|
back_color
|
0x0a
|
0x0a
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
cursor_color
|
cursor_color
|
0x0c
|
0x0c
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
vga
|
vga
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ext_mem
|
ext_mem
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
|
|
bank
|
bank
|
0x02
|
0x02
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
wait_st
|
wait_st
|
0x00
|
0x00
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
|
|
mem
|
mem
|
mb
|
mb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
vic
|
vic
|
0x10
|
0x10
|
8
|
8
|
|
|
|
|
|
|
int_in
|
int_in
|
0x00
|
0x00
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
irq_enable
|
irq_enable
|
0x02
|
0x02
|
8
|
8
|
read-write
|
read-write
|
|
|
|
|
|
|
|
|
irq_act
|
irq_act
|
0x06
|
0x06
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
irq_vec
|
irq_vec
|
0x08
|
0x08
|
8
|
8
|
read-only
|
read-only
|
|
|
|
|
|
|
|
|
vic
|
vic
|
mb
|
mb
|
|
|
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17
|
17
|
ext
|
ext
|
|
|
|
|
ext
|
ext
|
0x0000
|
0x0000
|
|
|
|
|
psram
|
psram
|
0x10000
|
0x10000
|
16
|
16
|
|
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