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Rev 134 |
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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opencores.org
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opencores.org
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io
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io
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io_vic
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io_vic
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def default
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def default
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slave_clk
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slave_clk
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clk
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clk
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clk
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clk
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slave_reset
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slave_reset
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reset
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reset
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reset
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reset
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mb
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mb
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little
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little
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8
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8
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rdata
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rdata
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rdata
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rdata
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wire
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wire
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70
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70
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addr
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addr
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addr
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addr
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30
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30
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wdata
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wdata
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wdata
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wdata
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70
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70
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rd
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rd
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rd
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rd
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wr
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wr
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wr
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wr
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cs
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cs
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cs
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cs
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elab_verilog
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102.1
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none
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:*Simulation:*
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./tools/verilog/elab_verilog
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dest_dir
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io_ports
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gen_registers
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gen_registers
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102.1
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102.1
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common
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common
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none
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none
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./tools/regtool/gen_registers
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./tools/regtool/gen_registers
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bus_intf
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bus_intf
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mb
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mb
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dest_dir
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dest_dir
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../verilog
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../verilog
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gen_verilog
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gen_verilog
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104.0
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104.0
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none
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none
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common
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common
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./tools/verilog/gen_verilog
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./tools/verilog/gen_verilog
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destination
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destination
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top
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io_vic_def
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dest_dir
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../verilog
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fs-common
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fs-common
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../verilog/top.body
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../verilog/top.body
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verilogSourcefragment
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verilogSourcefragment
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fs-sim
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fs-sim
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../verilog/copyright.v
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../verilog/copyright.v
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verilogSourceinclude
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verilogSourceinclude
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../verilog/common/top
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../verilog/common/io_vic_def
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verilogSourcemodule
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verilogSourcemodule
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mb
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mb
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../verilog/io_vic_def_mb
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../verilog/io_vic_def_mb
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verilogSourcemodule
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verilogSourcemodule
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Hierarchical
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Hierarchical
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spirit:library="io"
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spirit:library="io"
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spirit:name="io_vic"
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spirit:name="io_vic"
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spirit:version="def.design"/>
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spirit:version="def.design"/>
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verilog
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verilog
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spirit:library="Testbench"
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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spirit:version="verilog"/>
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commoncommon
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commoncommon
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Verilog
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Verilog
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fs-common
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fs-common
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sim:*Simulation:*
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sim:*Simulation:*
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Verilog
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Verilog
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fs-sim
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fs-sim
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syn:*Synthesis:*
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syn:*Synthesis:*
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Verilog
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Verilog
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fs-sim
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fs-sim
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doc
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doc
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spirit:library="Testbench"
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:name="toolflow"
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spirit:version="documentation"/>
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spirit:version="documentation"/>
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:*Documentation:*
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:*Documentation:*
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Verilog
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Verilog
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IRQ_MODE8'h00
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IRQ_MODE8'h00
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VEC_008'he0
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VEC_008'he0
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VEC_018'he2
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VEC_018'he2
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VEC_028'he4
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VEC_028'he4
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VEC_038'he6
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VEC_038'he6
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VEC_048'he8
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VEC_048'he8
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VEC_058'hea
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VEC_058'hea
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VEC_068'hec
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VEC_068'hec
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VEC_078'hee
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VEC_078'hee
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VEC_NONE8'h00
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VEC_NONE8'h00
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enable
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enable
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wire
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wire
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in
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in
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int_in
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int_in
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wire
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wire
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in
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in
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70
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70
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irq_out
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irq_out
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reg
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reg
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out
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out
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vector
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vector
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reg
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reg
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out
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out
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70
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70
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mb
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mb
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8
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8
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mb
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mb
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0x00
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0x00
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mb_microbus
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mb_microbus
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0x10
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0x10
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8
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8
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int_in
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int_in
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0x0
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0x0
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8
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8
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read-only
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read-only
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irq_enable
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irq_enable
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0x2
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0x2
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8
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8
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read-write
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read-write
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irq_act
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irq_act
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0x6
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0x6
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8
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8
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read-only
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read-only
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irq_vec
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irq_vec
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0x8
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0x8
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8
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8
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read-only
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read-only
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