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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_exp5.xml] - Diff between revs 133 and 134

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Rev 133 Rev 134
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
opencores.org
opencores.org
logic
logic
micro_bus
micro_bus
exp5  default
exp5  default
mb_out
mb_out
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
    
    
      
      
        addr
        addr
        
        
        addr_in
        addr_in
          70
          70
        
        
      
      
      
      
        rdata
        rdata
        
        
        rdata_out
        rdata_out
          150
          150
        
        
      
      
      
      
        wdata
        wdata
        
        
        wdata_in
        wdata_in
          70
          70
        
        
      
      
      
      
        rd
        rd
        
        
        rd_in
        rd_in
        
        
      
      
      
      
        wr
        wr
        
        
        wr_in
        wr_in
        
        
      
      
      
      
        cs
        cs
        
        
        cs_in
        cs_in
        
        
      
      
      
      
        wait
        wait
        
        
        wait_out
        wait_out
        reg
        reg
        
        
      
      
    
    
 
 
mas_0
mas_0
  
  
  
  
  
  
    
    
      
      
        addr
        addr
        
        
        mas_0_addr_out
        mas_0_addr_out
          30
          30
        
        
      
      
      
      
        rdata
        rdata
        
        
        mas_0_rdata_in
        mas_0_rdata_in
          70
          70
        
        
      
      
      
      
        wdata
        wdata
        
        
        mas_0_wdata_out
        mas_0_wdata_out
          70
          70
        
        
      
      
      
      
        rd
        rd
        
        
        mas_0_rd_out
        mas_0_rd_out
        
        
      
      
      
      
        wr
        wr
        
        
        mas_0_wr_out
        mas_0_wr_out
        
        
      
      
      
      
        cs
        cs
        
        
        mas_0_cs_out
        mas_0_cs_out
        
        
      
      
    
    
 
 
mas_1
mas_1
  
  
  
  
  
  
    
    
      
      
        addr
        addr
        
        
        mas_1_addr_out
        mas_1_addr_out
          30
          30
        
        
      
      
      
      
        rdata
        rdata
        
        
        mas_1_rdata_in
        mas_1_rdata_in
          70
          70
        
        
      
      
      
      
        wdata
        wdata
        
        
        mas_1_wdata_out
        mas_1_wdata_out
          70
          70
        
        
      
      
      
      
        rd
        rd
        
        
        mas_1_rd_out
        mas_1_rd_out
        
        
      
      
      
      
        wr
        wr
        
        
        mas_1_wr_out
        mas_1_wr_out
        
        
      
      
      
      
        cs
        cs
        
        
        mas_1_cs_out
        mas_1_cs_out
        
        
      
      
    
    
 
 
mas_2
mas_2
  
  
  
  
  
  
    
    
      
      
        addr
        addr
        
        
        mas_2_addr_out
        mas_2_addr_out
          30
          30
        
        
      
      
      
      
        rdata
        rdata
        
        
        mas_2_rdata_in
        mas_2_rdata_in
          70
          70
        
        
      
      
      
      
        wdata
        wdata
        
        
        mas_2_wdata_out
        mas_2_wdata_out
          70
          70
        
        
      
      
      
      
        rd
        rd
        
        
        mas_2_rd_out
        mas_2_rd_out
        
        
      
      
      
      
        wr
        wr
        
        
        mas_2_wr_out
        mas_2_wr_out
        
        
      
      
      
      
        cs
        cs
        
        
        mas_2_cs_out
        mas_2_cs_out
        
        
      
      
    
    
 
 
mas_3
mas_3
  
  
  
  
  
  
    
    
      
      
        addr
        addr
        
        
        mas_3_addr_out
        mas_3_addr_out
          30
          30
        
        
      
      
      
      
        rdata
        rdata
        
        
        mas_3_rdata_in
        mas_3_rdata_in
          70
          70
        
        
      
      
      
      
        wdata
        wdata
        
        
        mas_3_wdata_out
        mas_3_wdata_out
          70
          70
        
        
      
      
      
      
        rd
        rd
        
        
        mas_3_rd_out
        mas_3_rd_out
        
        
      
      
      
      
        wr
        wr
        
        
        mas_3_wr_out
        mas_3_wr_out
        
        
      
      
      
      
        cs
        cs
        
        
        mas_3_cs_out
        mas_3_cs_out
        
        
      
      
    
    
 
 
mas_4
mas_4
  
  
  
  
  
  
    
    
      
      
        addr
        addr
        
        
        mas_4_addr_out
        mas_4_addr_out
          30
          30
        
        
      
      
      
      
        rdata
        rdata
        
        
        mas_4_rdata_in
        mas_4_rdata_in
          70
          70
        
        
      
      
      
      
        wdata
        wdata
        
        
        mas_4_wdata_out
        mas_4_wdata_out
          70
          70
        
        
      
      
      
      
        rd
        rd
        
        
        mas_4_rd_out
        mas_4_rd_out
        
        
      
      
      
      
        wr
        wr
        
        
        mas_4_wr_out
        mas_4_wr_out
        
        
      
      
      
      
        cs
        cs
        
        
        mas_4_cs_out
        mas_4_cs_out
        
        
      
      
    
    
 
 
 
 
  elab_verilog
 
  102.1
 
  none
 
  :*Simulation:*
 
  ./tools/verilog/elab_verilog
 
    
 
    
 
      configuration
 
      exp_default
 
    
 
    
 
      dest_dir
 
      io_ports
 
    
 
  
 
 
 
 
 
 
 
 
 
  gen_verilog
  gen_verilog
  104.0
  104.0
  none
  none
  common
  common
  ./tools/verilog/gen_verilog
  ./tools/verilog/gen_verilog
    
    
    
    
      destination
      destination
      top.exp5
      micro_bus_exp5
    
 
    
 
      dest_dir
 
      ../verilog
 
    
    
  
  
  
  
    
    
      fs-common
      fs-common
      
      
        
        
        ../verilog/top.body.exp5
        ../verilog/top.body.exp5
        verilogSourcefragment
        verilogSourcefragment
      
      
    
    
    
    
      fs-sim
      fs-sim
      
      
        
        
        ../verilog/copyright.v
        ../verilog/copyright.v
        verilogSourceinclude
        verilogSourceinclude
      
      
      
      
        
        
        ../verilog/common/top.exp5
        ../verilog/common/micro_bus_exp5
        verilogSourcemodule
        verilogSourcemodule
      
      
    
    
    
    
      fs-syn
      fs-syn
      
      
        
        
        ../verilog/copyright.v
        ../verilog/copyright.v
        verilogSourceinclude
        verilogSourceinclude
      
      
      
      
        
        
        ../verilog/common/top.exp5
        ../verilog/common/micro_bus_exp5
        verilogSourcemodule
        verilogSourcemodule
      
      
    
    
  
  
      
      
              
              
              verilog
              verilog
              
              
              
              
                                   spirit:library="Testbench"
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
                                   spirit:version="verilog"/>
              
              
              
              
              
              
              commoncommon
              commoncommon
              Verilog
              Verilog
              
              
                     
                     
                            fs-common
                            fs-common
                     
                     
              
              
              
              
              sim:*Simulation:*
              sim:*Simulation:*
              Verilog
              Verilog
              
              
                     
                     
                            fs-sim
                            fs-sim
                     
                     
              
              
              
              
              syn:*Synthesis:*
              syn:*Synthesis:*
              Verilog
              Verilog
              
              
                     
                     
                            fs-syn
                            fs-syn
                     
                     
              
              
              
              
              doc
              doc
              
              
              
              
                                   spirit:library="Testbench"
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
                                   spirit:version="documentation"/>
              
              
              :*Documentation:*
              :*Documentation:*
              Verilog
              Verilog
              
              
      
      
clk
clk
wire
wire
in
in
reset
reset
wire
wire
in
in
enable
enable
wire
wire
in
in
   
   
   4
   4
   mb_out
   mb_out
  
  
     mas_0
     mas_0
     0x00
     0x00
   
   
  
  
     mas_1
     mas_1
     0x10
     0x10
   
   
  
  
     mas_2
     mas_2
     0x20
     0x20
   
   
  
  
     mas_3
     mas_3
     0x30
     0x30
   
   
  
  
     mas_4
     mas_4
     0x40
     0x40
   
   
   
   
     mas_0
     mas_0
     00
     00
      
      
       mas_0
       mas_0
       16
       16
       8
       8
     
     
   
   
   
   
     mas_1
     mas_1
     10
     10
      
      
       mas_1
       mas_1
       16
       16
       8
       8
     
     
   
   
   
   
     mas_2
     mas_2
     20
     20
      
      
       mas_2
       mas_2
       16
       16
       8
       8
     
     
   
   
   
   
     mas_3
     mas_3
     30
     30
      
      
       mas_3
       mas_3
       16
       16
       8
       8
     
     
   
   
   
   
     mas_4
     mas_4
     40
     40
      
      
       mas_4
       mas_4
       16
       16
       8
       8
     
     
   
   
   
   
  
  
    mas_0
    mas_0
    0x10
    0x10
    8
    8
  
  
  
  
    mas_1
    mas_1
    0x10
    0x10
    8
    8
  
  
  
  
    mas_2
    mas_2
    0x10
    0x10
    8
    8
  
  
  
  
    mas_3
    mas_3
    0x10
    0x10
    8
    8
  
  
  
  
    mas_4
    mas_4
    0x10
    0x10
    8
    8
  
  
 
 

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