URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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Rev 135 |
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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opencores.org
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opencores.org
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logic
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logic
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uart
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uart
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2
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2
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VARIANT
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VARIANT
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TestBenches
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sim
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testbenches
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testbench
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version
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Fpgas
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syn
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ise
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chip
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variant
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/doc
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/doc
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default
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default
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def
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def
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PRESCALE5'b01100
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PRESCALE5'b01100
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PRE_SIZE5
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PRE_SIZE5
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SIZE8
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SIZE8
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DIV0
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DIV0
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DIV_SIZE4
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DIV_SIZE4
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rxtx
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rxtx
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rxtx
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rxtx
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PRESCALE5'b01100
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PRESCALE5'b01100
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PRE_SIZE5
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PRE_SIZE5
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SIZE8
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SIZE8
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DIV0
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DIV0
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DIV_SIZE4
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DIV_SIZE4
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TX_FIFO_SIZE3
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TX_FIFO_SIZE3
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TX_FIFO_WORDS8
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TX_FIFO_WORDS8
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RX_FIFO_SIZE3
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RX_FIFO_SIZE3
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RX_FIFO_WORDS8
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RX_FIFO_WORDS8
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rx
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rx
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rx
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rx
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PRESCALE5'b01100
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PRESCALE5'b01100
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PRE_SIZE5
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PRE_SIZE5
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SIZE8
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SIZE8
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DIV0
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DIV0
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DIV_SIZE4
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DIV_SIZE4
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RX_FIFO_SIZE3
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RX_FIFO_SIZE3
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RX_FIFO_WORDS8
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RX_FIFO_WORDS8
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tx
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tx
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tx
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tx
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PRESCALE5'b01100
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PRESCALE5'b01100
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PRE_SIZE5
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PRE_SIZE5
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SIZE8
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SIZE8
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DIV0
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DIV0
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DIV_SIZE4
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DIV_SIZE4
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TX_FIFO_SIZE3
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TX_FIFO_SIZE3
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TX_FIFO_WORDS8
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TX_FIFO_WORDS8
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uart/sim
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uart/sim
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uart_def_tb
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uart_def_tb
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default
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default
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def_tb
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def_tb
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PERIOD40
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PERIOD40
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TIMEOUT100000
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TIMEOUT100000
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uart_defTB.test.dut
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uart_defTB.test.dut
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icaruscoverage
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icaruscoverage
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uart_rx_tb
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uart_rx_tb
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rx_tb
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rx_tb
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rx
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rx
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PERIOD40
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PERIOD40
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TIMEOUT100000
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TIMEOUT100000
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uart_rxTB.test.dut
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uart_rxTB.test.dut
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icaruscoverage
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icaruscoverage
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uart_tx_tb
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uart_tx_tb
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tx_tb
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tx_tb
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tx
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tx
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PERIOD40
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PERIOD40
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TIMEOUT100000
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TIMEOUT100000
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uart_txTB.test.dut
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uart_txTB.test.dut
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icaruscoverage
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icaruscoverage
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uart_rxtx_tb
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uart_rxtx_tb
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rxtx_tb
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rxtx_tb
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rxtx
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rxtx
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PERIOD40
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PERIOD40
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TIMEOUT100000
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TIMEOUT100000
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icarus
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icarus
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uart_def_lint
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uart_def_lint
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def_lint
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def_lint
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default
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default
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rtl_check
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rtl_check
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uart_rx_lint
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uart_rx_lint
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rx_lint
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rx_lint
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rx
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rx
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rtl_check
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rtl_check
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uart_tx_lint
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uart_tx_lint
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tx_lint
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tx_lint
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tx
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tx
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rtl_check
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rtl_check
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uart_rxtx_lint
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uart_rxtx_lint
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rxtx_lint
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rxtx_lint
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rxtx
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rxtx
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rtl_check
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rtl_check
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default
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default
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uart_def_lint
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uart_def_lint
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divide
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divide
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uart_def_lint
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uart_def_lint
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DIV1
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DIV1
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rx_default
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rx_default
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uart_rx_lint
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uart_rx_lint
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RX_FIFO_SIZE4
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RX_FIFO_SIZE4
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RX_FIFO_WORDS16
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RX_FIFO_WORDS16
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tx_default
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tx_default
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uart_tx_lint
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uart_tx_lint
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TX_FIFO_SIZE4
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TX_FIFO_SIZE4
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TX_FIFO_WORDS16
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TX_FIFO_WORDS16
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rxtx_default
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rxtx_default
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uart_rxtx_lint
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uart_rxtx_lint
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TX_FIFO_SIZE3
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TX_FIFO_SIZE3
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TX_FIFO_WORDS8
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TX_FIFO_WORDS8
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RX_FIFO_SIZE4
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RX_FIFO_SIZE4
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RX_FIFO_WORDS16
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RX_FIFO_WORDS16
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default
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default
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uart_def_tb
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uart_def_tb
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TIMEOUT3000000
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TIMEOUT3000000
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divide
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divide
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uart_def_tb
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uart_def_tb
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DIV1
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DIV1
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TIMEOUT3000000
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TIMEOUT3000000
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rx_default
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rx_default
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uart_rx_tb
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uart_rx_tb
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RX_FIFO_SIZE4
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RX_FIFO_SIZE4
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RX_FIFO_WORDS16
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RX_FIFO_WORDS16
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TIMEOUT3000000
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TIMEOUT3000000
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tx_default
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tx_default
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uart_tx_tb
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uart_tx_tb
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TX_FIFO_SIZE4
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TX_FIFO_SIZE4
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TX_FIFO_WORDS16
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TX_FIFO_WORDS16
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TIMEOUT3000000
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TIMEOUT3000000
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rxtx_default
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rxtx_default
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uart_rxtx_tb
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uart_rxtx_tb
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TX_FIFO_SIZE3
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TX_FIFO_SIZE3
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TX_FIFO_WORDS8
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TX_FIFO_WORDS8
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RX_FIFO_SIZE4
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RX_FIFO_SIZE4
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RX_FIFO_WORDS16
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RX_FIFO_WORDS16
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TIMEOUT3000000
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TIMEOUT3000000
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