OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [componentCfg.xml] - Diff between revs 134 and 135

Only display areas with differences | Details | Blame | View Log

Rev 134 Rev 135
-->
 
 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
opencores.org
opencores.org
logic
logic
uart
uart
2
2
_
_
_
_
_
_
VARIANT
VARIANT
 
 
 
 
 
  
 
   TestBenches
 
   sim
 
   testbenches
 
   testbench
 
   version
 
  
 
  
 
   Fpgas
 
   syn
 
   ise
 
   chip
 
   variant
 
  
 
 
 
 
 
 
 
 
/doc
/doc
 
 
   default
   default
   def
   def
                  
                  
                  PRESCALE5'b01100
                  PRESCALE5'b01100
                  PRE_SIZE5
                  PRE_SIZE5
                  SIZE8
                  SIZE8
                  DIV0
                  DIV0
                  DIV_SIZE4
                  DIV_SIZE4
                  
                  
          
          
 
 
   rxtx
   rxtx
   rxtx
   rxtx
                  
                  
                  PRESCALE5'b01100
                  PRESCALE5'b01100
                  PRE_SIZE5
                  PRE_SIZE5
                  SIZE8
                  SIZE8
                  DIV0
                  DIV0
                  DIV_SIZE4
                  DIV_SIZE4
                  TX_FIFO_SIZE3
                  TX_FIFO_SIZE3
                  TX_FIFO_WORDS8
                  TX_FIFO_WORDS8
                  RX_FIFO_SIZE3
                  RX_FIFO_SIZE3
                  RX_FIFO_WORDS8
                  RX_FIFO_WORDS8
                  
                  
          
          
 
 
   rx
   rx
   rx
   rx
                 
                 
                 PRESCALE5'b01100
                 PRESCALE5'b01100
                 PRE_SIZE5
                 PRE_SIZE5
                 SIZE8
                 SIZE8
                 DIV0
                 DIV0
                 DIV_SIZE4
                 DIV_SIZE4
                 RX_FIFO_SIZE3
                 RX_FIFO_SIZE3
                 RX_FIFO_WORDS8
                 RX_FIFO_WORDS8
                 
                 
          
          
 
 
   tx
   tx
   tx
   tx
                
                
                PRESCALE5'b01100
                PRESCALE5'b01100
                PRE_SIZE5
                PRE_SIZE5
                SIZE8
                SIZE8
                DIV0
                DIV0
                DIV_SIZE4
                DIV_SIZE4
                TX_FIFO_SIZE3
                TX_FIFO_SIZE3
                TX_FIFO_WORDS8
                TX_FIFO_WORDS8
                
                
          
          
 
 
uart/sim
uart/sim
uart_def_tb
uart_def_tb
default
default
def_tb
def_tb
    PERIOD40
    PERIOD40
    TIMEOUT100000
    TIMEOUT100000
  
  
  uart_defTB.test.dut
  uart_defTB.test.dut
  
  
  icaruscoverage
  icaruscoverage
uart_rx_tb
uart_rx_tb
rx_tb
rx_tb
rx
rx
    PERIOD40
    PERIOD40
    TIMEOUT100000
    TIMEOUT100000
  
  
  uart_rxTB.test.dut
  uart_rxTB.test.dut
  
  
  icaruscoverage
  icaruscoverage
uart_tx_tb
uart_tx_tb
tx_tb
tx_tb
tx
tx
    PERIOD40
    PERIOD40
    TIMEOUT100000
    TIMEOUT100000
  
  
  uart_txTB.test.dut
  uart_txTB.test.dut
  
  
  icaruscoverage
  icaruscoverage
uart_rxtx_tb
uart_rxtx_tb
rxtx_tb
rxtx_tb
rxtx
rxtx
    PERIOD40
    PERIOD40
    TIMEOUT100000
    TIMEOUT100000
  icarus
  icarus
uart_def_lint
uart_def_lint
def_lint
def_lint
default
default
  rtl_check
  rtl_check
uart_rx_lint
uart_rx_lint
rx_lint
rx_lint
rx
rx
  rtl_check
  rtl_check
uart_tx_lint
uart_tx_lint
tx_lint
tx_lint
tx
tx
  rtl_check
  rtl_check
uart_rxtx_lint
uart_rxtx_lint
rxtx_lint
rxtx_lint
rxtx
rxtx
  rtl_check
  rtl_check
default
default
uart_def_lint
uart_def_lint
divide
divide
uart_def_lint
uart_def_lint
DIV1
DIV1
rx_default
rx_default
uart_rx_lint
uart_rx_lint
RX_FIFO_SIZE4
RX_FIFO_SIZE4
RX_FIFO_WORDS16
RX_FIFO_WORDS16
tx_default
tx_default
uart_tx_lint
uart_tx_lint
TX_FIFO_SIZE4
TX_FIFO_SIZE4
TX_FIFO_WORDS16
TX_FIFO_WORDS16
rxtx_default
rxtx_default
uart_rxtx_lint
uart_rxtx_lint
TX_FIFO_SIZE3
TX_FIFO_SIZE3
TX_FIFO_WORDS8
TX_FIFO_WORDS8
RX_FIFO_SIZE4
RX_FIFO_SIZE4
RX_FIFO_WORDS16
RX_FIFO_WORDS16
default
default
uart_def_tb
uart_def_tb
TIMEOUT3000000
TIMEOUT3000000
divide
divide
uart_def_tb
uart_def_tb
DIV1
DIV1
TIMEOUT3000000
TIMEOUT3000000
rx_default
rx_default
uart_rx_tb
uart_rx_tb
RX_FIFO_SIZE4
RX_FIFO_SIZE4
RX_FIFO_WORDS16
RX_FIFO_WORDS16
TIMEOUT3000000
TIMEOUT3000000
tx_default
tx_default
uart_tx_tb
uart_tx_tb
TX_FIFO_SIZE4
TX_FIFO_SIZE4
TX_FIFO_WORDS16
TX_FIFO_WORDS16
TIMEOUT3000000
TIMEOUT3000000
rxtx_default
rxtx_default
uart_rxtx_tb
uart_rxtx_tb
TX_FIFO_SIZE3
TX_FIFO_SIZE3
TX_FIFO_WORDS8
TX_FIFO_WORDS8
RX_FIFO_SIZE4
RX_FIFO_SIZE4
RX_FIFO_WORDS16
RX_FIFO_WORDS16
TIMEOUT3000000
TIMEOUT3000000
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.