URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_rx_tb.xml] - Diff between revs 131 and 134

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Rev 131	Rev 134

	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`

`opencores.org`	`opencores.org`
`logic`	`logic`
`uart`	`uart`
`rx_tb`	`rx_tb`









`gen_verilog`	`gen_verilog`
`104.0`	`104.0`
`none`	`none`
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.rx_tb`	`uart_rx_tb`


`dest_dir`
`../verilog`


`top`















`UART_MODEL_CLKCNT4'hc`	`UART_MODEL_CLKCNT4'hc`
`UART_MODEL_SIZE4`	`UART_MODEL_SIZE4`
`DIVIDER4'b0000`	`DIVIDER4'b0000`






`Params`	`Params`


`spirit:library="logic"`	`spirit:library="logic"`
`spirit:name="uart"`	`spirit:name="uart"`
`spirit:version="rx_dut.params"/>`	`spirit:version="rx_dut.params"/>`





`Bfm`	`Bfm`

`spirit:library="logic"`	`spirit:library="logic"`
`spirit:name="uart"`	`spirit:name="uart"`
`spirit:version="bfm.design"/>`	`spirit:version="bfm.design"/>`





`icarus`	`icarus`


`spirit:library="Testbench"`	`spirit:library="Testbench"`
`spirit:name="toolflow"`	`spirit:name="toolflow"`
`spirit:version="icarus"/>`	`spirit:version="icarus"/>`








`commoncommon`	`commoncommon`
`Verilog`	`Verilog`


`fs-common`	`fs-common`






`sim:Simulation:`	`sim:Simulation:`
`Verilog`	`Verilog`


`fs-sim`	`fs-sim`





`lint:Lint:`	`lint:Lint:`
`Verilog`	`Verilog`


`fs-lint`	`fs-lint`























`fs-common`	`fs-common`



`../verilog/tb.ext`	`../verilog/tb.ext`
`verilogSourcefragment`	`verilogSourcefragment`







`fs-sim`	`fs-sim`



`../verilog/common/top.rx_tb`	`../verilog/common/uart_rx_tb`
`verilogSourcemodule`	`verilogSourcemodule`








`fs-lint`	`fs-lint`



`../verilog/common/top.rx_tb`	`../verilog/common/uart_rx_tb`
`verilogSourcemodule`	`verilogSourcemodule`

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_rx_tb.xml] - Diff between revs 131 and 134