URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Only display areas with differences |
Details |
Blame |
View Log
Rev 131 |
Rev 135 |
|
|
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
wishbone
|
wishbone
|
wb_model
|
wb_model
|
master default
|
master
|
|
|
|
|
|
|
|
|
|
|
|
|
wb
|
wb
|
|
|
|
|
|
|
|
|
|
|
|
|
adr
|
|
|
|
adr
|
|
wb_addr_width-10
|
|
|
|
|
|
|
|
|
|
|
adr
|
|
|
|
adr
|
|
wb_addr_width-10
|
|
|
|
|
|
|
|
|
wdata
|
|
|
|
dout
|
|
wb_data_width-10
|
|
|
|
|
|
|
|
|
|
|
wdata
|
|
|
|
dout
|
|
wb_data_width-10
|
|
|
|
|
|
|
|
|
rdata
|
|
|
|
din
|
|
wb_data_width-10
|
|
|
|
|
|
|
|
|
|
|
rdata
|
|
|
|
din
|
|
wb_data_width-10
|
|
|
|
|
|
|
|
|
sel
|
|
|
|
sel
|
|
|
|
|
|
|
|
|
|
|
sel
|
|
|
|
sel
|
|
|
|
|
|
|
|
|
ack
|
|
|
|
ack
|
|
|
|
|
|
|
|
|
|
|
ack
|
|
|
|
ack
|
|
|
|
|
|
|
|
|
cyc
|
|
|
|
cyc
|
|
|
|
|
|
|
|
|
|
|
cyc
|
|
|
|
cyc
|
|
|
|
|
|
|
|
|
|
|
stb
|
|
|
|
stb
|
|
|
|
|
|
|
|
|
|
|
stb
|
|
|
|
stb
|
|
|
|
|
|
|
|
|
we
|
|
|
|
we
|
|
|
|
|
|
|
|
|
|
|
we
|
|
|
|
we
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilogLib_sim
|
|
105.0
|
|
none
|
|
:*Simulation:*
|
|
./tools/verilog/gen_verilogLib
|
|
|
|
|
|
dest_dir
|
|
../views
|
|
|
|
|
|
|
|
view
|
|
sim
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilogLib_syn
|
|
105.0
|
|
none
|
|
:*Synthesis:*
|
|
./tools/verilog/gen_verilogLib
|
|
|
|
|
|
dest_dir
|
|
../views
|
|
|
|
|
|
|
|
view
|
|
syn
|
|
|
|
|
|
|
|
|
|
|
gen_verilogLib_sim
|
|
105.0
|
|
none
|
|
:*Simulation:*
|
|
tools/verilog/gen_verilogLib
|
|
|
|
|
|
dest_dir
|
|
../views
|
|
|
|
|
|
|
|
view
|
|
sim
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilogLib_syn
|
|
105.0
|
|
none
|
|
:*Synthesis:*
|
|
tools/verilog/gen_verilogLib
|
|
|
|
|
|
dest_dir
|
|
../views
|
|
|
|
|
|
|
|
view
|
|
syn
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/top.sim
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
verilog
|
|
verilog
|
|
wb_model_master
|
|
|
|
|
|
awidth
|
|
32
|
|
|
|
|
|
dwidth
|
|
32
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/top.syn
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
dest_dir../views/syn/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
rtl
|
|
verilog:Kactus2:
|
|
verilog
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
dwidth32
|
|
awidth32
|
|
|
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
clk
|
|
wire
|
|
in
|
|
|
|
|
|
reset
|
doc
|
wire
|
|
in
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
adr
|
|
reg
|
|
out
|
|
awidth-10
|
|
|
|
|
|
|
|
dout
|
|
reg
|
|
out
|
|
dwidth0
|
|
|
|
|
|
|
dwidth32
|
|
awidth32
|
|
|
|
|
|
|
cyc
|
|
reg
|
|
out
|
|
|
|
|
clk
|
stb
|
wire
|
reg
|
in
|
out
|
|
|
|
|
reset
|
we
|
wire
|
reg
|
in
|
out
|
|
|
|
|
adr
|
|
reg
|
|
out
|
|
awidth-10
|
|
|
|
|
|
|
sel
|
|
reg
|
|
out
|
|
dwidth/8-10
|
|
|
|
|
dout
|
|
reg
|
|
out
|
|
dwidth0
|
|
|
|
|
|
|
din
|
|
wire
|
|
in
|
|
dwidth-10
|
|
|
|
|
cyc
|
|
reg
|
|
out
|
|
|
|
|
|
stb
|
ack
|
reg
|
wire
|
out
|
in
|
|
|
|
|
we
|
err
|
reg
|
wire
|
out
|
in
|
|
|
|
|
|
rty
|
|
wire
|
|
in
|
|
|
|
|
sel
|
|
reg
|
|
out
|
|
dwidth/8-10
|
|
|
|
|
|
|
|
|
|
din
|
|
wire
|
|
in
|
|
dwidth-10
|
|
|
|
|
|
|
|
ack
|
|
wire
|
|
in
|
|
|
|
|
|
err
|
|
wire
|
|
in
|
|
|
|
|
|
rty
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/top.sim
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/top.syn
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
dest_dir../views/syn/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.