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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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opencores.org
|
opencores.org
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wishbone
|
wishbone
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wb_uart16550
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wb_uart16550
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bus32_big_tb
|
bus32_big_tb
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gen_verilog
|
gen_verilog
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104.0
|
104.0
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none
|
none
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common
|
common
|
./tools/verilog/gen_verilog
|
./tools/verilog/gen_verilog
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destination
|
destination
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top.bus32_big_tb
|
wb_uart16550_bus32_big_tb
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dest_dir
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../verilog
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top
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UART_MODEL_CLKCNT4'b1100
|
UART_MODEL_CLKCNT4'b1100
|
UART_MODEL_SIZE4
|
UART_MODEL_SIZE4
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Params
|
Params
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spirit:library="wishbone"
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spirit:library="wishbone"
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spirit:name="wb_uart16550"
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spirit:name="wb_uart16550"
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spirit:version="bus32_big_dut.params"/>
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spirit:version="bus32_big_dut.params"/>
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Bfm
|
Bfm
|
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|
spirit:library="wishbone"
|
spirit:library="wishbone"
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spirit:name="wb_uart16550"
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spirit:name="wb_uart16550"
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spirit:version="bfm.design"/>
|
spirit:version="bfm.design"/>
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|
icarus
|
icarus
|
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|
spirit:library="Testbench"
|
spirit:library="Testbench"
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spirit:name="toolflow"
|
spirit:name="toolflow"
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spirit:version="icarus"/>
|
spirit:version="icarus"/>
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headersheaders
|
headersheaders
|
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|
Verilog
|
Verilog
|
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commoncommon
|
commoncommon
|
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|
Verilog
|
Verilog
|
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fs-common
|
fs-common
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|
sim:*Simulation:*
|
sim:*Simulation:*
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|
|
Verilog
|
Verilog
|
|
|
|
|
fs-sim
|
fs-sim
|
|
|
|
|
|
|
|
|
lint:*Lint:*
|
lint:*Lint:*
|
Verilog
|
Verilog
|
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|
fs-lint
|
fs-lint
|
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fs-common
|
fs-common
|
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|
../verilog/tb.ext
|
../verilog/tb.ext
|
verilogSourcefragment
|
verilogSourcefragment
|
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|
fs-sim
|
fs-sim
|
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|
../verilog/common/top.bus32_big_tb
|
../verilog/common/wb_uart16550_bus32_big_tb
|
verilogSourcemodule
|
verilogSourcemodule
|
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|
|
|
|
|
fs-lint
|
fs-lint
|
|
|
|
|
|
|
../verilog/common/top.bus32_big_tb
|
../verilog/common/wb_uart16550_bus32_big_tb
|
verilogSourcemodule
|
verilogSourcemodule
|
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