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Rev 134 |
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module mt45w8mw12_def
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#(
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parameter ADDR_BITS = 23,
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parameter DQ_BITS = 16,
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parameter MEM_BITS = 16
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)
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(
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input wire clk,
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input wire adv_n,
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input wire cre,
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output wire o_wait,
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input wire ce_n,
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input wire oe_n,
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input wire we_n,
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input wire lb_n,
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input wire ub_n,
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input wire [ADDR_BITS-1 : 0] addr,
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inout wire [DQ_BITS-1 : 0] dq
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);
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reg [7:0] memoryl [1<<MEM_BITS-1:0];
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reg [7:0] memoryl [1<<MEM_BITS-1:0];
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reg [7:0] memoryu [1<<MEM_BITS-1:0];
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reg [7:0] memoryu [1<<MEM_BITS-1:0];
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reg [DQ_BITS-1 : 0] dq_out;
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reg [DQ_BITS-1 : 0] dq_out;
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// Write Memory
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// Write Memory
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// Read Memory
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// Read Memory
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always@(*) dq_out[7:0] = 8'h0;
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always@(*) dq_out[7:0] = 8'h0;
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always@(*) dq_out[15:8] = 8'h0;
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always@(*) dq_out[15:8] = 8'h0;
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// Tristate output
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// Tristate output
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// assign dq = (!ce_n && !oe_n) ? dq_out[DQ_BITS-1:0]: {DQ_BITS{1'bz}};
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// assign dq = (!ce_n && !oe_n) ? dq_out[DQ_BITS-1:0]: {DQ_BITS{1'bz}};
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endmodule
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