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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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opencores.org
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opencores.org
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Testbench
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Testbench
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uart_model
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uart_model
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def default
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def default
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elab_verilog
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102.1
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none
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:*Simulation:*
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./tools/verilog/elab_verilog
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dest_dir
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io_ports
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gen_verilog_sim
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gen_verilog_sim
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104.0
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104.0
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none
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none
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:*Simulation:*
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:*Simulation:*
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./tools/verilog/gen_verilog
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./tools/verilog/gen_verilog
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destination
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destination
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top.out.sim
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uart_model_def
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dest_dir
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../verilog
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gen_verilog_syn
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gen_verilog_syn
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104.0
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104.0
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none
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none
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:*Synthesis:*
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:*Synthesis:*
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./tools/verilog/gen_verilog
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./tools/verilog/gen_verilog
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destination
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destination
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top.out.syn
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uart_model_def
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dest_dir
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../verilog
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Hierarchical
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spirit:library="Testbench"
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spirit:name="uart_model"
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spirit:version="def.design"/>
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verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-syn
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doc
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="documentation"/>
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:*Documentation:*
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Verilog
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CLKCNT4'h5
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SIZE4
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clk
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wire
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in
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reset
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wire
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in
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txd_in
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wire
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in
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rxd_out
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wire
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out
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gen_verilogLib_sim
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105.0
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none
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:*Simulation:*
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./tools/verilog/gen_verilogLib
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dest_dir
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../views
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view
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sim
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gen_verilogLib_syn
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105.0
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none
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:*Synthesis:*
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./tools/verilog/gen_verilogLib
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dest_dir
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../views
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view
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syn
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fs-sim
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fs-sim
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../verilog/copyright.v
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../verilog/copyright
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verilogSourceinclude
|
verilogSourceinclude
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../verilog/sim/top.out.sim
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../verilog/top.rtl
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verilogSourcemodule
|
verilogSourcefragment
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../verilog/top.rtl
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../verilog/top.tasks
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verilogSourcefragment
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verilogSourcefragment
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../verilog/top.tasks
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../verilog/sim/uart_model_def
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verilogSourcefragment
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verilogSourcemodule
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../verilog/serial_rcvr
|
../verilog/serial_rcvr
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verilogSourcemodule
|
verilogSourcemodule
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../verilog/serial_xmit
|
../verilog/serial_xmit
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verilogSourcemodule
|
verilogSourcemodule
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../verilog/divider
|
../verilog/divider
|
verilogSourcemodule
|
verilogSourcemodule
|
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dest_dir../views/sim/
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dest_dir../views/sim/
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verilogSourcelibraryDir
|
verilogSourcelibraryDir
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fs-syn
|
fs-syn
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../verilog/copyright.v
|
../verilog/copyright
|
verilogSourceinclude
|
verilogSourceinclude
|
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../verilog/syn/top.out.syn
|
../verilog/top.rtl
|
verilogSourcemodule
|
verilogSourcefragment
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../verilog/top.rtl
|
../verilog/serial_rcvr
|
verilogSourcefragment
|
verilogSourcemodule
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../verilog/serial_rcvr
|
../verilog/syn/uart_model_def
|
verilogSourcemodule
|
verilogSourcemodule
|
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../verilog/serial_xmit
|
../verilog/serial_xmit
|
verilogSourcemodule
|
verilogSourcemodule
|
|
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|
../verilog/divider
|
../verilog/divider
|
verilogSourcemodule
|
verilogSourcemodule
|
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|
dest_dir../views/syn/
|
dest_dir../views/syn/
|
verilogSourcelibraryDir
|
verilogSourcelibraryDir
|
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|
|
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|
|
Hierarchical
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="uart_model"
|
|
spirit:version="def.design"/>
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKCNT4'h5
|
|
SIZE4
|
|
|
|
|
|
|
|
|
|
clk
|
|
wire
|
|
in
|
|
|
|
|
|
reset
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
txd_in
|
|
wire
|
|
in
|
|
|
|
|
|
rxd_out
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
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|
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|
