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Rev 134 |
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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opencores.org
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opencores.org
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cde
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cde
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clock
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clock
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sys default
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sys default
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clock
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clock
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clk
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clk
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div_clk_out
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div_clk_out
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reset
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reset
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reset
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reset
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reset
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reset
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gen_verilog
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104.0
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none
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common
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./tools/verilog/gen_verilog
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destination
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clock_sys
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Hierarchical
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Hierarchical
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spirit:library="cde"
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spirit:library="cde"
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spirit:name="clock"
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spirit:name="clock"
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spirit:version="sys.design"/>
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spirit:version="sys.design"/>
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verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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commoncommon
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Verilog
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fs-common
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sim:*Simulation:*
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sim:*Simulation:*
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Verilog
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Verilog
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fs-sim
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fs-sim
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syn:*Synthesis:*
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syn:*Synthesis:*
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Verilog
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Verilog
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fs-syn
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fs-syn
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doc
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doc
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spirit:library="Testbench"
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:name="toolflow"
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spirit:version="documentation"/>
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spirit:version="documentation"/>
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:*Documentation:*
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:*Documentation:*
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Verilog
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Verilog
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FREQ48
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FREQ48
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PLL_MULT2
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PLL_MULT2
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PLL_DIV4
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PLL_DIV4
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PLL_SIZE4
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PLL_SIZE4
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CLOCK_SRC0
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CLOCK_SRC0
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RESET_SENSE0
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RESET_SENSE0
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a_clk_pad_in
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a_clk_pad_in
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wire
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wire
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in
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in
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b_clk_pad_in
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b_clk_pad_in
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wire
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wire
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in
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in
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pwron_pad_in
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pwron_pad_in
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wire
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wire
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in
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in
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div_clk_out
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div_clk_out
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reg
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wire
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out
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out
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one_usec
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one_usec
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reg
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reg
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out
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out
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reset
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reset
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wire
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wire
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out
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out
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fs-common
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../verilog/clock_sys
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verilogSourcefragment
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fs-sim
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fs-sim
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../verilog/copyright
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verilogSourceinclude
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../verilog/common/clock_sys
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verilogSourcemodule
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dest_dir
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dest_dir
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../verilog/
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../views/sim/
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verilogSource
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verilogSource
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libraryDir
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libraryDir
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fs-syn
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fs-syn
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../verilog/copyright
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verilogSourceinclude
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../verilog/common/clock_sys
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verilogSourcemodule
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dest_dir
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dest_dir
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../verilog/
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../views/syn/
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verilogSource
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verilogSource
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libraryDir
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libraryDir
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fs-lint
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fs-lint
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dest_dir
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dest_dir
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../verilog/
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../views/syn/
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verilogSourcelibraryDir
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verilogSourcelibraryDir
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