URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Go to most recent revision |
Only display areas with differences |
Details |
Blame |
View Log
| Rev 131 |
Rev 134 |
|
|
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
cde
|
cde
|
divider
|
divider
|
def default
|
def default
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog
|
|
104.0
|
|
none
|
|
common
|
|
./tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
divider_def
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
dest_dir
|
|
../verilog/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
dest_dir
|
|
../verilog/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-lint
|
|
|
|
dest_dir
|
|
../verilog/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
commoncommon
|
|
Verilog
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
sim:*Simulation:*
|
Verilog
|
Verilog
|
|
|
|
|
fs-sim
|
fs-sim
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
syn:*Synthesis:*
|
Verilog
|
Verilog
|
|
|
|
|
fs-syn
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
doc
|
doc
|
|
|
|
|
spirit:library="Testbench"
|
spirit:library="Testbench"
|
spirit:name="toolflow"
|
spirit:name="toolflow"
|
spirit:version="documentation"/>
|
spirit:version="documentation"/>
|
|
|
:*Documentation:*
|
:*Documentation:*
|
Verilog
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SIZE4
|
SIZE4
|
SAMPLE0
|
SAMPLE0
|
RESET1
|
RESET1
|
|
|
|
|
|
|
|
|
clk
|
clk
|
wire
|
wire
|
in
|
in
|
|
|
|
|
reset
|
reset
|
wire
|
wire
|
in
|
in
|
|
|
|
|
|
|
enable
|
enable
|
wire
|
wire
|
in
|
in
|
|
|
|
|
|
|
|
|
|
|
divider_in
|
divider_in
|
wire
|
wire
|
in
|
in
|
SIZE-10
|
SIZE-10
|
|
|
|
|
|
|
divider_out
|
divider_out
|
reg
|
reg
|
out
|
out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
../verilog/divider_def
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/common/divider_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
dest_dir
|
|
../views/sim/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/common/divider_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
dest_dir
|
|
../views/syn/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-lint
|
|
|
|
dest_dir
|
|
../views/syn/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.