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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg ex_freeze_r;
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reg ex_freeze_r;
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always @( posedge clk)
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always @( posedge clk)
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if (reset) ex_freeze_r <= 1'b1;
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if (reset) ex_freeze_r <= 1'b1;
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else ex_freeze_r <= ex_freeze;
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else ex_freeze_r <= ex_freeze;
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wire [2*WIDTH-1:0] mul_prod;
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wire [2*WIDTH-1:0] mul_prod;
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reg [1:0] mul_stall_count;
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reg [1:0] mul_stall_count;
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`ifndef SYNTHESYS
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`ifndef SYNTHESIS
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always@(posedge clk)
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always@(posedge clk)
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if(mul_stall_count == 2'b10)
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if(mul_stall_count == 2'b10)
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begin
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begin
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$display("%t %m mul (%x,%x,%x);",$realtime,a_in,b_in,mul_prod );
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$display("%t %m mul (%x,%x,%x);",$realtime,a_in,b_in,mul_prod );
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end
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end
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`endif
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`endif
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or1200_gmultp2_32x32 or1200_gmultp2_32x32(
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or1200_gmultp2_32x32 or1200_gmultp2_32x32(
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.X(a_in),
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.X(a_in),
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.Y(b_in),
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.Y(b_in),
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.RST(reset),
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.RST(reset),
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.CLK(clk),
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.CLK(clk),
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.P(mul_prod)
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.P(mul_prod)
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);
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);
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always @( posedge clk)
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always @( posedge clk)
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if (reset) begin
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if (reset) begin
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mul_prod_r <= 64'h0000_0000_0000_0000;
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mul_prod_r <= 64'h0000_0000_0000_0000;
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end
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end
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else begin
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else begin
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mul_prod_r <= mul_prod[63:0];
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mul_prod_r <= mul_prod[63:0];
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end
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end
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//
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//
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// Generate stall signal during multiplication
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// Generate stall signal during multiplication
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//
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//
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always @( posedge clk)
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always @( posedge clk)
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if (reset)
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if (reset)
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mul_stall_count <= 0;
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mul_stall_count <= 0;
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else if (!(|mul_stall_count))
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else if (!(|mul_stall_count))
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mul_stall_count <= {mul_stall_count[0], alu_op_mul & !ex_freeze_r};
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mul_stall_count <= {mul_stall_count[0], alu_op_mul & !ex_freeze_r};
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else
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else
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mul_stall_count <= {mul_stall_count[0],1'b0};
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mul_stall_count <= {mul_stall_count[0],1'b0};
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assign mul_stall = (|mul_stall_count) |
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assign mul_stall = (|mul_stall_count) |
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(!(|mul_stall_count) & alu_op_mul & !ex_freeze_r);
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(!(|mul_stall_count) & alu_op_mul & !ex_freeze_r);
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